Nanotechnology For Electronics, Photonics, Biosensors, And Emerging Technologies

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Оглавление
Группа авторов. Nanotechnology For Electronics, Photonics, Biosensors, And Emerging Technologies
NANOTECHNOLOGY FOR ELECTRONICS, PHOTONICS, BIOSENSORS, AND EMERGING TECHNOLOGIES
Preface
Contents
References
Results
Conclusions
References
1. Introduction
2. Methodology. 2.1. Thin film
2.2. Carbon nanotubes
2.3. Scanning electron microscope
3. Results. 3.1. Thin film
3.2. Nanoparticles
3.3. Density
3.4. Carbon Nanotubes
4. Conclusion. 4.1. Thin Film Deposition and Thickness
4.2. Nanoparticles
4.3. Carbon Nanotubes
5. Summary/Future Work. 5.1. Summary
5.2. Future Work
Acknowledgements
Appendix A. TPVD Trials
Appendix B. CVD Trials
Appendix C. Pressure Gauge Conversion Table
Appendix D. Outliers
References
1. Introduction
2. On the Device Scale: The Internet of Skins and Origami based RF Structures
3. On the Package Scale: On-Package Antennas
4. On the Die Scale: 3D/Inkjet Printed Interconnects
5. On the Component Scale: Fully printed sensors and passive components
6. Future Works and Conclusion
Acknowledgements
References
1. Introduction
2. Plastic Flow Model (DTKA Model)
3. Results and Discussion
4. Conclusion
References
1. Introduction to 2-Bit Logic using SWS-FET
2. Fast-erase low-voltage QD-NVRAMs
3. Enhanced number of bits in a 2-channel SWS-FET configured as QD-NVRAM and as a multi-state QDG-FET for Logic
4. Multipliers and Adders using quaternary SWS-FETs
5. In-Memory digital and analog computing
6. Conclusion
Acknowledgments
References
1. Introduction
2. Blockchain Architecture
3. Blockchain Integrity through Consensus and the 51% attack
4. Solutions to mitigate the 51% Attack. 4.1. Proof of Stake (POS) Consensus Methods
4.2. Permissioned vs. Permission-less Blockchain
4.3. Private Transaction Implementation for Parity Ethereum, and Quorum implementations
4.4. Second Factor Authentication (2FA) for Smart Contract
5. Conclusion
References
1. Introduction
2. Experimental and Characterization
3. Results
4. Conclusion
References
1. Introduction
2. Transformable Electronics Implantation in ROM
3. Design Methodology
3.1. Mg via/contact placements by considering crosstalk noise between bitlines
3.2. MgO via/contact placements by considering read failures
3.3. MgO via/contact placements by considering read failures
4. Evaluation
4.1. Via-Programming ROMs
4.2. ROM Cell Withs Double-Rail Bitline Scheme
5. Conclusion
References
1. Introduction
2. Preliminaries
3. Partial Reconfiguration based FPGA Bitstream Decryption. 3.1. Motivation
3.2. The Proposed Design
3.3. Updated CAD flow
3.4. FPGA platform compatibility
4. Implementation and Results
4.1. Circuit Implementation
4.2. Resource Utilization
4.3. Performance Analysis
5. Conclusion
References
1. Introduction
2. Experimental
3. Results and Discussion
4. Conclusion
References
1. Introduction to 2-Bit CMOS SWS Inverter
2. 2-bit SWS SRAMs
3. Enhanced number of bits in a 4-channel SWS-FET configured as and as a 8-state SWS-CMOS Inverter
4. Latches and registers using 2-bit SWS-SRAMs
5. Integration of QD-NVRAMs, SRAMs, Registers, and Adders using SWS-FETs
6. Conclusion
Acknowledgments
References
1. Introduction
2. Experimental QD-SWS-FET
3. ABM Simulation
4. ABM Simulation Code for Interface
5. Conclusion
Acknowledgments
References
1. Introduction
2. Experimental QDG-FET
3. Quantum Simulations
4. Verilog Model and Simulations
5. ABM Simulation
6. ABM Simulation Code for Interface
7. Conclusion
Acknowledgments
References
Отрывок из книги
SELECTED TOPICS IN ELECTRONICS AND SYSTEMS
Editor-in-Chief: M. S. Shur ISSN: 1793-1274
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Vol. 52: Frontiers in Electronics Proceedings of the Workshop on Frontiers in Electronics 2009 (WOFE-2009) eds. Sorin Cristoloveanu and Michael S. Shur
*The complete list of the published volumes in the series can be found at
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