Electronic Packaging Science and Technology
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Оглавление
King-Ning Tu. Electronic Packaging Science and Technology
Table of Contents
List of Tables
List of Illustrations
Guide
Pages
Electronic Packaging Science and Technology
Preface
1 Introduction. 1.1 Introduction
1.2 Impact of Moore’s Law on Si Technology
1.3 5G Technology and AI Applications
1.4 3D IC Packaging Technology
1.5 Reliability Science and Engineering
1.6 The Future of Electronic Packaging Technology
1.7 Outline of the Book
References
2 Cu‐to‐Cu and Other Bonding Technologies in Electronic Packaging. 2.1 Introduction
2.2 Wire Bonding
2.3 Tape‐Automated Bonding
2.4 Flip‐Chip Solder Joint Bonding
2.5 Micro‐Bump Bonding
2.6 Cu‐to‐Cu Direct Bonding
2.6.1 Critical Factors for Cu‐to‐Cu Bonding
2.6.2 Analysis of Cu‐to‐Cu Bonding Mechanism
2.6.3 Microstructures at the Cu‐to‐Cu Bonding Interface
2.7 Hybrid Bonding
2.8 Reliability – Electromigration and Temperature Cycling Tests
Problems
References
3 Randomly‐Oriented and (111) Uni‐directionally‐Oriented Nanotwin Copper. 3.1 Introduction
3.2 Formation Mechanism of Nanotwin Cu
3.3 In Situ Measurement of Stress Evolution During Nanotwin Deposition
3.4 Electrodeposition of Randomly Oriented Nanotwinned Copper
3.5 Formation of Unidirectionally (111)‐oriented Nanotwin Copper
3.6 Grain Growth in [111]‐Oriented nt‐Cu
3.7 Uni‐directional Growth of η‐Cu6Sn5 in Microbumps on (111) Oriented nt‐Cu
3.8 Low Thermal‐Budget Cu‐to‐Cu Bonding Using [111]‐Oriented nt‐Cu
3.9 Nanotwin Cu RDL for Fanout Package and 3D IC Integration
Problems
References
4 Solid–Liquid Interfacial Diffusion Reaction (SLID) Between Copper and Solder. 4.1 Introduction
4.2 Kinetics of Scallop‐Type IMC Growth in SLID
4.3 A Simple Model for the Growth of Mono‐Size Hemispheres
4.4 Theory of Flux‐Driven Ripening
4.5 Measurement of the Nano‐channel Width Between Two Scallops
4.6 Extremely Rapid Grain Growth in Scallop‐Type Cu6Sn5 in SLID
Problems
References
5 Solid‐State Reactions Between Copper and Solder. 5.1 Introduction
5.2 Layer‐Type Growth of IMC in Solid‐State Reactions
5.3 Wagner Diffusivity
5.4 Kirkendall Void Formation in Cu3Sn
5.5 Sidewall Reaction to Form Porous Cu3Sn in μ‐Bumps
5.6 Effect of Surface Diffusion on IMC Formation in Pillar‐Type μ‐Bumps
Problems
References
6 Essence of Integrated Circuits and Packaging Design. 6.1 Introduction
6.2 Transistor and Interconnect Scaling
6.3 Circuit Design and LSI
6.4 System‐on‐Chip (SoC) and Multicore Architectures
6.5 System‐in‐Package (SiP) and Package Technology Evolution
6.6 3D IC Integration and 3D Silicon Integration
6.7 Heterogeneous Integration: An Introduction
Problems
References
7 Performance, Power, Thermal, and Reliability. 7.1 Introduction
7.2 Field‐Effect Transistor and Memory Basics
7.3 Performance: A Race in Early IC Design
7.4 Trend in Low Power
7.5 Trade‐off between Performance and Power
7.6 Power Delivery and Clock Distribution Networks
7.7 Low‐Power Design Architectures
7.8 Thermal Problems in IC and Package
7.9 Signal Integrity and Power Integrity (SI/PI)
7.10 Robustness: Reliability and Variability
Problems
References
8 2.5D/3D System‐in‐Packaging Integration. 8.1 Introduction
8.2 2.5D IC: Redistribution Layer (RDL) and TSV‐Interposer
8.3 2.5D IC: Silicon, Glass, and Organic Substrates
8.4 2.5D IC: HBM on Silicon Interposer
8.5 3D IC: Memory Bandwidth Challenge for High‐Performance Computing
8.6 3D IC: Electrical and Thermal TSVs
8.7 3D IC: 3D‐Stacked Memory and Integrated Memory Controller
8.8 Innovative Packaging for Modern Chips/Chiplets
8.9 Power Distribution for 3D IC Integration
8.10 Challenge and Trend
Problems
References
9 Irreversible Processes in Electronic Packaging Technology. 9.1 Introduction
9.2 Flow in Open Systems
9.3 Entropy Production
9.3.1 Electrical Conduction
9.3.1.1 Joule Heating
9.3.2 Atomic Diffusion
9.3.3 Heat Conduction
9.3.4 Conjugate Forces When Temperature Is a Variable
9.4 Cross‐Effects in Irreversible Processes
9.5 Cross‐Effect Between Atomic Diffusion and Electrical Conduction
9.5.1 Electromigration and Stress‐Migration in Al Strips
9.6 Irreversible Processes in Thermomigration
9.6.1 Thermomigration in Unpowered Composite Solder Joints
9.7 Cross‐Effect Between Heat Conduction and Electrical Conduction
9.7.1 Seebeck Effect
9.7.2 Peltier Effect
Problems
References
10 Electromigration. 10.1 Introduction
10.2 To Compare the Parameters in Atomic Diffusion and Electric Conduction
10.3 Basic of Electromigration
10.3.1 Electron Wind Force
10.3.2 Calculation of the Effective Charge Number
10.3.3 Atomic Flux Divergence Induced Electromigration Damage
10.3.4 Back Stress in Electromigration
10.4 Current Crowding and Electromigration in 3‐Dimensional Circuits
10.4.1 Void Formation in the Low Current Density Region
10.4.2 Current Density Gradient Force in Electromigration
10.4.3 Current Crowding Induced Pancake‐Type Void Formation in Flip‐Chip Solder Joints
10.5 Joule Heating and Heat Dissipation
10.5.1 Joule Heating and Electromigration
10.5.2 Joule Heating on Mean‐Time‐to‐Failure in Electromigration
Problems
References
11 Thermomigration. 11.1 Introduction
11.2 Driving Force of Thermomigration
11.3 Analysis of Heat of Transport, Q*
11.4 Thermomigration Due to Heat Transfer Between Neighboring Pairs of Powered and Unpowered Solder Joints
Problems
References
12 Stress‐Migration. 12.1 Introduction
12.2 Chemical Potential in a Stressed Solid
12.3 Stoney’s Equation of Biaxial Stress in Thin Films
12.4 Diffusional Creep
12.5 Spontaneous Sn Whisker Growth at Room Temperature. 12.5.1 Morphology
12.5.2 Measurement of the Driving Force to Grow a Sn Whisker
12.5.3 Kinetics of Sn Whisker Growth
12.5.4 Electromigration‐Induced Sn Whisker Growth in Solder Joints
12.6 Comparison of Driving Forces Among Electromigration, Thermomigration, and Stress‐Migration
12.6.1 Products of Force
Problems
References
13 Failure Analysis. 13.1 Introduction
13.2 Microstructure Change with or Without Lattice Shift
13.3 Statistical Analysis of Failure. 13.3.1 Black’s Equation of MTTF for Electromigration
13.3.2 Weibull Distribution Function and JMA Theory of Phase Transformations
13.4 A Unified Model of MTTF for Electromigration, Thermomigration, and Stress‐Migration. 13.4.1 Revisit Black’s Equation of MTTF for Electromigration
13.4.2 MTTF for Thermomigration
13.4.3 MTTF for Stress‐Migration
13.4.4 The Link Among MTTF for Electromigration, Thermomigration, and Stress‐Migration
13.4.5 MTTF Equations for Other Irreversible Processes in Open Systems
13.5 Failure Analysis in Mobile Technology
13.5.1 Joule Heating Enhanced Electromigration Failure of Weak‐Link in 2.5D IC Technology
13.5.2 Joule Heating Induced Thermomigration Failure Due to Thermal Crosstalk in 2.5D IC Technology
Problems
References
14 Artificial Intelligence in Electronic Packaging Reliability. 14.1 Introduction
14.2 To Change Time‐Dependent Event to Time‐Independent Event
14.3 To Deduce MTTF from Mean Microstructure Change to Failure
14.4 Summary
Index. a
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King‐Ning Tu
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Figure 1.4 Scanning electron microscopy (SEM) image of the cross‐section of a 3D IC test device. It has only two pieces of Si chips stacking on a polymer board.
In the interposer, there are arrays of vertical through‐Si‐vias (TSV) plated with Cu, making connections to the third arrays of solder joints of diameter about 10–20 μm, the so‐called micro‐bumps or μ‐bumps, which join the interposer to the top Si chip. The top Si chip is an active device chip, so it has transistors. The thickness of the device in Figure 1.4 is about that of a US penny. The thinness of the device is a critical requirement due to the limit of form factor of mobile consumer electronic products. Consequently, the thickness of Si chips is thin too. The thickness of the Si interposer is about 50 μm, which is much thinner than that of a convention Si chip of 200 μm in thickness. The thin interposer has caused the warpage problem, as well as the heat conduction issue, to be discussed in the later chapters. The diameter of the TSV in the interposer is about 5 μm, so the aspect ratio of the TSV is 10.
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