Оглавление
Peter D. Minns. Digital System Design using FSMs
Table of Contents
List of Tables
List of Illustrations
Guide
Pages
Digital System Design using FSMs. A Practical Learning Approach
Preface
Acknowledgements
About the Companion Website
Guide to Supplementary Resources
1 Introduction to Finite State Machines
1.1 SOME NOTES ON STYLE
Frame 1.1 What is a Finite State Machine?
Frame 1.2
Frame 1.3
Frame 1.4
Frame 1.5
Frame 1.6
Frame 1.7
Frame 1.8
Frame 1.9
Frame 1.10
Frame 1.11
Frame 1.12
Frame 1.13
Frame 1.14
Frame 1.15
Moore and Mealy state diagram
Frame 1.16
Frame 1.17
Frame 1.18
Frame 1.19
Frame 1.20
Frame 1.21 The Timing Waveform Diagram Solution
Frame 1.22
2 Using FSMs to Control External Devices. 2.1 INTRODUCTION
Frame 2.1
Frame 2.2
Frame 2.3
Frame 2.4
Controlling an analogue‐to‐digital converter (ADC)
Frame 2.5
Frame 2.6
Frame 2.7
Frame 2.8
Frame 2.9
Frame 2.10
Frame 2.11
Frame 2.12
Frame 2.13
Frame 2.14
Note
3 Introduction to FSM Synthesis
3.1 INTRODUCTION
Frame 3.1 The T Type Flip‐Flop
Frame 3.2 The T Flip‐Flop Example
Frame 3.3
Frame 3.4
Frame 3.5
Time state problem
Memory control problem
Data acquisition problem
Frame 3.6
Timer state problem
Memory control problem
Data acquisition problem
Frame 3.7
Frame 3.8
Frame 3.9
Frame 3.10
Frame 3.11 Another Look at the D Type Flip‐Flop Rules
Frame 3.12
Frame 3.13
Frame 3.14
Frame 3.15
Frame 3.16 Resetting the Flip‐Flops
Frame 3.17
Timer problem
Memory control problem
Data acquisition problem
Frame 3.18 Solutions to the Problems in Frame 3.17
Timer problem
Memory control problem
Data acquisition problem
Frame 3.19
The design equations
Frame 3.20
The specification
Frame 3.21
The design equations
Testing your solution is important
Frame 3.22
Frame 3.23
Another note on propagation delays in FSM systems
3.2 TUTORIALS COVERING CHAPTERS 1, 2, AND 3. 3.2.1 Binary data serial transmitter FSM
3.2.2 The high low FSM system
3.2.3 The clocked watchdog timer FSM
3.2.3.1 FSM equations
3.2.4 The asynchronous receiver system clocked FSM
3.2.4.1 Brief note on the development of the test bench generator
3.2.4.2 The state diagram
3.2.4.3 The state diagram equations
3.2.4.4 The outputs
3.2.4.5 Verilog HDL simulation of the completed system
4 Asynchronous FSM Methods. 4.1 INTRODUCTION TO ASYNCHRONOUS FSM
Frame 4.1
Frame 4.2
Frame 4.3
Frame 4.4
Frame 4.5
Frame 4.6
Frame 4.7
Frame 4.8
Frame 4.9
Frame 4.10
Frame 4.11
Frame 4.12
Frame 4.13
Frame 4.14
Frame 4.15
Frame 4.16
Frame 4.17
Frame 4.18
Frame 4.19 Using the Short Cut Rule
Frame 4.20
Frame 4.21
Frame 4.22
Frame 4.23 With Mealy output R
Frame 4.24
Frame 4.25
Frame 4.26
Frame 4.27
Frame 4.28
Frame 4.29
Frame 4.30
Frame 4.31
Frame 4.32
Frame 4.33
Frame 4.34
Frame 4.35
Frame 4.36
Frame 4.37
Frame 4.38
Frame 4.39
Frame 4.40
Frame 4.41
Frame 4.42
Frame 4.43
Frame 4.44 Looking at the State Diagram Figure 4.19
Frame 4.45
Frame 4.46 Using Relays in FSM Design
Frame 4.47
Frame 4.48
Frame 4.49
Frame 4.50 FSM Outputs
Frame 4.51
Frame 4.52
Frame 4.53
Frame 4.54
Frame 4.55
Frame 4.56 Future Work with FSM‐based Systems
4.2 SUMMARY
4.3 TUTORIALS
4.3.1 FSM motor with fault detection
4.3.2 The mower in four and two states
Important note
5 Clocked One Hot Method of FSM Design. 5.1 INTRODUCTION
Frame 5.1
Frame 5.2
Frame 5.3
Frame 5.4
Frame 5.5
Frame 5.6
Frame 5.7
Frame 5.8
Frame 5.9
Frame 5.10
Frame 5.11
Frame 5.12
Frame 5.13
Frame 5.14
Frame 5.15
Frame 5.16
Frame 5.17
Frame 5.18
Frame 5.19
Frame 5.20
Frame 5.21
5.2 TUTORIALS ON THE CLOCKED ONE HOT FSM METHOD
5.2.1 Seven‐state system clocked one hot method
5.2.2 Memory tester FSM
Listing 5.1 Memory tester FSM
5.2.3 Eight‐bit sequence detector FSM
6 Further Event‐Driven FSM Design. 6.1 INTRODUCTION
Frame 6.1
Frame 6.2
Frame 6.3
Frame 6.4
Frame 6.5
Problems caused by propagation delays
Frame 6.6. Unused states
Frame 6.7
Frame 6.8
Frame 6.9 Motor Problem with Fault
Frame 6.10
Frame 6.11
Frame 6.12 Introducing the Event‐Driven One Hot Method
Frame 6.13 The Three‐Handshake FSM System
6.2 CONCLUSIONS
Note
7 Petri Net FSM Design. 7.1 INTRODUCTION
Frame 7.1
Frame 7.2
Frame 7.3
Frame 7.4
Frame 7.5
Frame 7.6
Frame 7.7
Frame 7.8
Frame 7.9
Frame 7.10
Frame 7.11
Frame 7.12
Frame 7.13
Frame 7.14
Frame 7.15
Frame 7.16
Frame 7.17
Frame 7.18
Frame 7.19
Frame 7.20
Frame 7.21
Frame 7.22
Frame 7.23
Frame 7.24
Frame 7.25
Frame 7.26
Frame 7.27
Frame 7.28
Frame 7.29
Frame 7.30
Frame 7.31
Frame 7.32
Frame 7.33
Frame 7.34
Frame 7.35
Frame 7.36
Frame 7.37
Frame 7.38
Frame 7.39
Frame 7.40
Frame 7.41
Frame 7.42
Frame 7.43
Frame 7.44
7.2 TUTORIALS USING PETRI NET FSM
7.2.1 Controlled shared resource Petri nets
7.2.2 Serial clock‐driven Petri net FSM
The Petri net equations
Petri net 1
Petri net 2
7.2.3 Using asynchronous (event‐driven) design with Petri nets
7.3 CONCLUSIONS
Appendix A1: Boolean Algebra
A1.1 BASIC GATE SYMBOLS
A1.2 THE EXCLUSIVE OR AND EXCLUSIVE NOR
A1.3 LAWS OF BOOLEAN ALGEBRA
A1.3.1 Basic OR rules
A1.3.2 Basic AND rules
A1.3.3 Associative and commutative laws
A1.3.4 Distributive laws
A1.3.5 Auxiliary rule for static 1 hazard removal
A1.3.5.1 Proof of the Auxiliary Rule
A1.3.6 Consensus theorem
A1.3.7 The effect of signal delay in logic gates
A1.3.8 De‐Morgan’s theorem
A1.4 EXAMPLES OF APPLYING THE LAWS OF BOOLEAN ALGEBRA. A1.4.1 Converting AND–OR to NAND
A1.4.2 Converting AND–OR to NOR
A1.4.3 Logical adjacency rule
A1.5 SUMMARY
Appendix A2: Use of Verilog HDL and Logisim to FSM
A2.1 THE SINGLE‐PULSE GENERATOR WITH MEMORY CLOCK‐DRIVEN FSM
A2.2 TEST BENCH MODULE AND ITS PURPOSE
A2.3 USING SYNAPTICAD SOFTWARE
A2.4 MORE DIRECT METHOD
A2.5 A VERY SIMPLE GUIDE TO USING THE LOGISIM SIMULATOR. A2.5.1 The Logisim top level menu items
A2.6 USING FLIP‐FLOPS IN A CIRCUIT
A2.7 EXAMPLE SINGLE‐PULSE FSM
A2.8 HOW TO USE THE SIMULATOR TO SIMULATE THE SINGLE‐PULSE FSM
A2.8.1 Using Logisim with the truth table approach
A2.9 USING LOGISIM WITH THE TRUTH TABLE APPROACH
A2.9.1 Useful note
A2.10 SUMMARY
Note
Appendix A3: Counters, Shift Registers, Input, and Output with an FSM
A3.1 BASIC DOWN SYNCHRONOUS BINARY COUNTER DEVELOPMENT
A3.2 EXAMPLE OF A FOUR‐BIT SYNCHRONOUS UP COUNTER WITH T TYPE FLIP‐FLOPS
A3.3 PARALLEL LOADING COUNTERS – USING T FLIP‐FLOPS
A3.4 USING D FLIP‐FLOPS TO BUILD PARALLEL LOADING COUNTERS
A3.5 SIMPLE BINARY UP COUNTER WITH PARALLEL INPUTS
A3.6 CLOCK CIRCUIT TO DRIVE THE COUNTER (AND FSM)
A3.7 COUNTER DESIGN USING DON’T CARE STATES
A3.8 SHIFT REGISTERS
A3.9 DEALING WITH INPUT AND OUTPUT SIGNALS USING FSM
A3.10 USING LOGISIM TO WORK WITH LARGER FSM SYSTEMS
A3.10.1 The equations
A3.11 SUMMARY
Note
Appendix A4: Finite State Machines Using Verilog Behavioural Mode. A4.1 INTRODUCTION
A4.2 THE SINGLE‐PULSE/MULTIPLE‐PULSE GENERATOR WITH MEMORY FSM
A4.3 THE MEMORY TESTER FSM REVISITED
A4.4 SUMMARY
Appendix A5: Programming a Finite State Machine. A5.1 INTRODUCTION
A5.2 THE PARALLEL LOADING COUNTER
A5.3 THE MULTIPLEXER
A5.4 THE MICRO INSTRUCTION
A5.5 THE MEMORY
A5.6 THE INSTRUCTION SET
A5.7 SIMPLE EXAMPLE: SINGLE‐PULSE FSM
A5.8 THE FINAL EXAMPLE
A5.9 THE PROGRAM CODE
A5.10 RETURNING UNUSED STATES VIA OTHER TRANSITION PATHS
A5.11 SUMMARY
Appendix A6: The Rotational Detector Using Logisim Simulator with Sub‐Circuits
A6.1 USING THE TWO‐STATE DIAGRAM ARRANGEMENT
Bibliography. REFERENCES
FURTHER READING
Index
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