Оглавление
Tsai-Fu Wu. Origin of Power Converters
Table of Contents
List of Tables
List of Illustrations
Guide
Pages
Origin of Power Converters. Decoding, Synthesizing, and Modeling
Preface
Acknowledgments
About the Authors
1 Introduction
1.1 Power Processing Systems
1.2 Non‐PWM Converters Versus PWM Converters
1.2.1 Non‐PWM Converters
1.2.2 PWM Power Converters
1.3 Well‐Known PWM Converters
1.4 Approaches to Converter Development
1.5 Evolution
1.6 About the Text
1.6.1 Part I: Decoding and Synthesizing
1.6.2 Part II: Modeling and Applications
Further Reading
2 Discovery of Original Converter
2.1 Creation of Original Converter
2.1.1 Source–Load Approach
2.1.2 Proton–Neutron–Meson Analogy
2.1.3 Resonance Approach
2.2 Fundamental PWM Converters
2.2.1 Voltage Transfer Ratios
2.2.2 CCM Operation
2.2.3 DCM Operation
2.2.4 Inverse Operation
2.3 Duality
Further Reading
3 Fundamentals
3.1 DC Voltage and Current Offsetting
3.1.1 DC Voltage Offsetting
3.1.2 DC Current Offsetting
3.2 Capacitor and Inductor Splitting
3.3 DC‐Voltage Blocking and Pulsating‐Voltage Filtering
3.4 Magnetic Coupling
3.5 DC Transformer
3.6 Switch Grafting
3.7 Diode Grafting
3.8 Layer Scheme
Further Reading
4 Decoding Process
4.1 Transfer Ratios (Codes)
4.2 Transfer Code Configurations
4.2.1 Cascade Configuration
4.2.2 Feedback Configuration
4.2.3 Feedforward Configuration
4.2.4 Parallel Configuration
4.3 Decoding Approaches
4.3.1 Factorization
4.3.2 Long Division
4.3.3 Cross Multiplication
4.4 Decoding of Transfer Codes with Multivariables
4.5 Decoding with Component‐Interconnected Expression
Further Reading
5 Synthesizing Process with Graft Scheme
5.1 Cell Approaches
5.1.1 P‐Cell and N‐Cell
5.1.2 Tee Canonical Cell and Pi Canonical Cell
5.1.3 Switched‐Capacitor Cell and Switched‐Inductor Cell
5.1.4 Inductor–Capacitor Component Cells
5.2 Converter Grafting Scheme
5.2.1 Synchronous Switch Operation
5.2.2 Grafting Active Switches
5.2.3 Grafting Passive Switches
5.3 Illustration of Grafting Converters
5.3.1 Grafting the Well‐Known PWM Converters
5.3.1.1 Graft Boost on Buck
5.3.1.2 Graft Buck on Boost
5.3.1.3 Graft Buck on Buck–Boost
5.3.1.4 Graft Boost on Boost–Buck
5.3.1.5 Buck in Parallel with Buck–Boost
5.3.1.6 Grafting Buck on Buck to Achieve High Step‐Down Voltage Conversion
5.3.1.7 Grafting Boost on Boost to Achieve High Step‐up Voltage Conversion
5.3.1.8 Grafting Boost (CCM) on Buck (DCM)
5.3.1.9 Cascode Complementary Zeta with Buck
5.3.2 Grafting Various Types of Converters
5.3.2.1 Grafting Half‐Bridge Resonant Inverter on Dither Boost Converter
5.3.2.2 Grafting Half‐Bridge Resonant Inverter on Bidirectional Flyback Converter
5.3.2.3 Grafting Class‐E Converter on Boost Converter
5.3.3 Integrating Converters with Active and Passive Grafted Switches
5.3.3.1 Grafting Buck on Boost with Grafted Diode
5.3.3.2 Grafting Half‐Bridge Inverter on Interleaved Boost Converters in DCM
5.3.3.3 Grafting N‐Converters with TGS
5.3.3.4 Grafting N‐Converters with ΠGS
Further Reading
6 Synthesizing Process with Layer Scheme
6.1 Converter Layering Scheme
6.2 Illustration of Layering Converters
6.2.1 Buck Family
6.2.2 Boost Family
6.2.3 Other Converter Examples
6.3 Discussion
6.3.1 Deduction from Ćuk to Buck–Boost
6.3.2 Deduction from Sepic to Buck–Boost
6.3.3 Deduction from Zeta to Buck–Boost
6.3.4 Deduction from Sepic to Zeta
Further Reading
7 Converter Derivation with the Fundamentals
7.1 Derivation of Buck Converter
7.1.1 Synthesizing with Buck–Boost Converter
7.1.2 Synthesizing with Ćuk Converter
7.2 Derivation of z‐Source Converters
7.2.1 Voltage‐Fed z‐Source Converters
7.2.1.1 Synthesizing with Sepic Converter
7.2.1.2 Synthesizing with Zeta Converter
7.2.2 Current‐Fed z‐Source Converters
7.2.2.1 Synthesizing with SEPIC Converter
7.2.2.2 Synthesizing with Zeta Converter
7.2.3 Quasi‐z‐Source Converter
7.2.3.1 Synthesizing with Sepic Converter
7.2.3.2 Synthesizing with Zeta Converter
7.3 Derivation of Converters with Switched Inductor or Switched Capacitor
7.3.1 Switched‐Inductor Converters
7.3.1.1 High Step‐Down Converter with Transfer Code D/(2 − D)
7.3.1.2 High Step‐Down Converter with Transfer Code D/(2(1 − D))
7.3.1.2.1 Synthesis with SEPIC and I‐Ćuk
7.3.1.2.2 Synthesis with Zeta and I‐Buck–Boost
7.3.1.2.3 Synthesis with SEPIC and I‐Buck–Boost
7.3.1.2.4 Synthesis with Zeta and I‐Ćuk
7.3.2 Switched‐Capacitor Converters
7.3.2.1 High Step‐Up Converter with Transfer Code (1 + D)/(1 − D)
7.3.2.2 High Step‐Up Converter with Transfer Code 2D/(1 − D)
7.3.2.3 High Step‐Up Converter with Transfer Code D/(1 − 2D)
7.4 Syntheses of Desired Transfer Codes
7.4.1 Synthesis of Transfer Code: D2/(D2 − 3D + 2)
7.4.1.1 Synthesizing with Buck–Boost Converter
7.4.1.2 Synthesizing with Zeta Converter
7.4.1.3 Synthesizing with Ćuk Converter
7.4.2 Synthesizing Converters with the Fundamentals
7.4.2.1 DC Voltage and DC Current Offsetting
7.4.2.2 Inductor and Capacitor Splitting
7.4.2.3 DC Voltage Blocking and Filtering
7.4.2.4 Magnetic Coupling
7.4.2.5 DC Transformer
7.4.2.6 Switch and Diode Grafting
7.4.2.7 Layer Technique
Further Reading
8 Synthesis of Multistage and Multilevel Converters
8.1 Review of the Original Converter and Its Variations of Transfer Code
8.2 Syntheses of Single‐Phase Converters
8.3 Syntheses of Three‐Phase Converters
8.4 Syntheses of Multilevel Converters
8.5 L–C Networks
Further Reading
9 Synthesis of Soft‐Switching PWM Converters
9.1 Soft‐Switching Cells
9.1.1 Passive Lossless Soft‐Switching Cells
9.1.1.1 Near‐Zero‐Current Switching Mechanism
9.1.1.2 Near‐Zero‐Voltage Switching Mechanism
9.1.2 Active Lossless Soft‐Switching Cells
9.1.2.1 Zero‐Voltage Switching Mechanism
9.1.2.2 Zero‐Current Switching Mechanism
9.2 Synthesis of Soft‐Switching PWM Converters with Graft Scheme
9.2.1 Generation of Passive Soft‐Switching PWM Converters
9.2.2 Generation of Active Soft‐Switching PWM Converters
9.3 Synthesis of Soft‐Switching PWM Converters with Layer Scheme
9.3.1 Generation of Passive Soft‐Switching PWM Converters
9.3.2 Generation of Active Soft‐Switching PWM Converters
9.4 Discussion
Further Reading
10 Determination of Switch‐Voltage Stresses
10.1 Switch‐Voltage Stress of the Original Converter
10.2 Switch‐Voltage Stresses of the Fundamental Converters
10.2.1 The Six Well‐Known PWM Converters
10.2.1.1 Boost Converter
10.2.1.2 Buck–Boost Converter
10.2.1.3 Ćuk, Sepic, and Zeta Converters
10.2.2 z‐Source Converters
10.2.2.1 Voltage‐Fed z‐Source Converter
10.2.2.2 Current‐Fed z‐Source Converter
10.2.2.3 Quasi‐z‐Source Converter
10.3 Switch‐Voltage Stresses of Non‐Fundamental Converters
10.3.1 High Step‐Down Switched‐Inductor Converter
10.3.2 High Step‐Down/Step‐Up Switched‐Inductor Converter
10.3.3 Compound Step‐Down/Step‐Up Switched‐Capacitor Converter
10.3.4 High Step‐Down Converter with Transfer Ratio of D2
10.3.5 High Step‐Up Converter with Transfer Ratio of 1/(1 −D)2
Further Reading
11 Discussion and Conclusion
11.1 Will Identical Transfer Code Yield the Same Converter Topology?
11.2 Topological Duality Versus Circuital Duality
11.3 Graft and Layer Schemes for Synthesizing New Fundamental Converters
11.3.1 Synthesis of Buck–Boost Converter
11.3.2 Synthesis of Boost–Buck (Ćuk) Converter
11.3.3 Synthesis of Buck–Boost–Buck (Zeta) Converter
11.3.4 Synthesis of Boost–Buck–Boost (Sepic) Converter
11.3.5 Synthesis of Buck‐Family Converters with Layer Scheme
11.3.6 Synthesis of Boost‐Family Converters with Layer Scheme
11.4 Analogy of Power Converters to DNA
11.4.1 Replication
11.4.2 Mutation
11.5 Conclusions
Notes:
Further Reading
12 Modeling of PWM DC/DC Converters
12.1 Generic Modeling of the Original Converter
12.2 Series‐Shunt and Shunt‐Series Pairs
12.3 Two‐Port Network
12.4 Small‐Signal Modeling of the Converters Based on Layer Scheme
12.5 Quasi‐Resonant Converters
Further Reading
13 Modeling of PWM DC/DC Converters Using the Graft Scheme
13.1 Cascade Family
13.2 Small‐Signal Models of Buck‐Boost and Ćuk Converters Operated in CCM
13.2.1 Buck‐Boost Converter
13.2.2 Boost‐Buck Converter
13.3 Small‐Signal Models of Zeta and Sepic Operated in CCM
13.3.1 Zeta Converter
13.3.2 Sepic Converter
Further Reading
14 Modeling of Isolated Single‐Stage Converters with High Power Factor and Fast Regulation
14.1 Generation of Single‐Stage Converters with High Power Factor and Fast Regulation
14.2 Small‐Signal Models of General Converter Forms Operated in CCM/DCM
14.3 An Illustration Example
Further Reading
15 Analysis and Design of an Isolated Single‐Stage Converter Achieving Power Factor Correction and Fast Regulation
15.1 Derivation of the Single‐Stage Converter
15.1.1 Selection of Individual Semi‐Stages
15.1.2 Derivation of the Discussed Isolated Single‐Stage Converter
15.2 Analysis of the Isolated Single‐Stage Converter Operated in DCM + DCM
15.2.1 Buck‐Boost Power Factor Corrector
15.2.2 Flyback Regulator
15.3 Design of a Peak Current Mode Controller for the ISSC
15.4 Practical Consideration and Design Procedure. 15.4.1 Component Stress
15.4.2 Snubber Circuit
15.4.3 Design Procedure
15.5 Hardware Measurements
15.6 Design of an H∞ Robust Controller for the ISSC. 15.6.1 H∞ Control
15.6.2 An Illustration Example of Robust Control and Hardware Measurements
Further Reading
Index. a
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