Читать книгу Multi-Processor System-on-Chip 1 - Liliana Andrade - Страница 29

Cyber-physical systems (CPSs) are characterized by software that interacts with the physical world, often with time-sensitive safety-critical physical sensing and actuation (Lee et al. 2017). Applications such as aircraft pilot support or automated driving systems require more than what classical CPSs provide. More specifically, application functionality increasingly relies on machine learning techniques, while cyber-security requirements have become significantly more stringent. We refer to CPSs enhanced with high-performance machine learning capabilities and strong cyber-security support as “intelligent systems”. Given the state of CMOS computing technology (Kanduri et al. 2017), providing the processing performances required by intelligent systems while meeting the size, weight and power (SWaP) constraints of embedded systems can only be achieved by parallel computing and the specialization of processing elements. For example, automated driving systems targeting L3/L4 SAE J3016 levels of automation are estimated to require over 150 TOPS of deep learning inference in vehicle perception functions, while motion planning functions would require more than 50 FP32 TFLOPS (Figure 2.5).

In order to address the challenges of high-performance embedded computing with time predictability, Kalray has been refining a many-core architecture called the MPPA (Massively Parallel Processor Array) across three generations. The first-generation MPPA processor was primarily targeting accelerated computing (Dupont de Dinechin et al. 2013), but implemented the first key architectural features for time-critical computing (Dupont de Dinechin et al. 2014). Kalray further improved the second-generation MPPA processor for time predictability (Saidi et al. 2015), providing an excellent target for model-based code generation (Perret et al. 2016; Graillat et al. 2018, 2019). Accurate analysis of network-on-chip (NoC) service guarantees was achieved through a new deterministic network calculus formulation (Dupont de Dinechin and Graillat 2017). Unlike the first-generation MPPA processor that relied on cyclostatic dataflow programming (Bodin et al. 2013, 2016), the second-generation MPPA programming environment was able to support OpenCL and OpenVX applications (Hascoët et al. 2018).

In this chapter, we present the third-generation MPPA processor, manufactured in 16FFC CMOS technology, whose many-core architecture has significantly improved upon the previous ones in the areas of performance, programmability, functional safety and cyber-security. These features are motivated by application cases in defense, avionics and automotive where the high-performance, high-integrity and cyber-security functions can be consolidated onto a single or dual processor configuration. In section 2.2, we discuss many-core architectures and their limitations with regard to intelligent system requirements. In section 2.3, we present the main features of the third-generation MPPA architecture and processor. In section 2.4, we introduce the MPPA3 application software environments.