Читать книгу Reversible and DNA Computing - Hafiz M. H. Babu - Страница 30

The delay of each 1 1 and 2 2 reversible gate is taken as unit delay 1. Any 3 3 reversible gate can be designed from 1 1 reversible gates and 2 2 reversible gates, such as CNOT gate, controlled‐V, and controlled‐ gates (V is a square root of NOT gate and is its hermitian). Thus, the delay of a 3 3 reversible gate can be computed by calculating its logical depth when it is designed from smaller 1 1 and 2 2 reversible gates.