Читать книгу Quantum Computing - Hafiz Md. Hasan Babu - Страница 4
Contents
Оглавление1 Quantum logic
1.2 Motivations towards quantum computing
1.3 The relationship between reversible and quantum logic
1.5 The working principles of quantum computers
1.6 The evolution of quantum computers
1.7 Why pursue quantum computing?
2 Basic definitions of quantum logic
2.2.1 The quantum Feynman gate
2.2.2 The quantum Tofolli gate
2.2.3 The quantum Fredkin gate
2.10 Quantum gate calculation complexity
3 The quantum bit string comparator
3.1 Characteristics of a comparator
3.3 The design of a quantum comparator
4 The quantum adder and subtractor
4.2.1 The quantum half-subtractor
4.2.2 The quantum full-subtractor
5 The quantum multiplexer and demultiplexer
5.1.1 The quantum 2-to-1 multiplexer
5.1.2 The quantum 4-to-1 multiplexer
5.1.3 The quantum 2n-to-1 multiplexer
5.2.1 The quantum 1-to-2 demultiplexer
5.2.2 The quantum 1-to-4 demultiplexer
5.2.3 The quantum 1-to-2n demultiplexer
6 Quantum adder circuits
6.2 The quantum comparison circuit
6.3 The quantum 2-to-1 multiplier circuit
6.4 The design of a quantum carry skip adder
6.4.1 The four-bit quantum carry skip adder
6.4.2 The n-bit quantum carry skip adder
6.4.3 Calculation of the area and power of a quantum carry skip adder circuit
6.4.4 Complexity of the n-bit quantum carry skip adder circuit
7 The quantum multiplier–accumulator
7.1 The importance of the quantum multiplier–accumulator
7.2 The multiplication technique
7.3 Reduction of the garbage outputs and ancillary inputs of quantum circuits
7.4 The design of a quantum multiplier circuit
7.4.1 The quantum ANDing circuit
7.4.2 The quantum full-adder circuit
7.4.3 The n × n-qubit quantum multiplier
8 The quantum divider
8.1.1 Classical integer division algorithms
8.1.2 Quantum integer division algorithms
8.2 The importance of the quantum divider
8.3 The tree-based quantum division technique
8.3.1 Definitions and properties of the division technique
8.3.2 The algorithm of the division technique
8.4 The design of a quantum divider circuit
8.4.1 A technique to minimize the number of ancillary inputs in the quantum circuit realization
8.4.2 The components of the quantum divider circuit
9 The quantum BCD priority encoder
9.1 The properties of an encoder
9.2 The design of a quantum BCD priority encoder circuit
9.2.1 The quantum BCD priority encoder circuit
9.2.2 Analysis of the properties of the encoder circuit
10 The quantum decoder
10.1 The characteristics of a decoder
10.2 The design of a quantum decoder
10.2.1 The quantum decoder circuit
10.2.2 Analysis of the properties of the circuits
11 The quantum square root circuit
11.1 Properties of a square root function
11.2 The design of a quantum square root circuit
11.2.1 The quantum adder/subtractor circuit
11.2.2 The quantum square root circuit
11.2.3 Analysis of the properties of the circuit
12 Quantum latches and counter circuits
12.2 The design of the quantum latches
12.3 Properties of counter circuits
12.4 The design of the quantum counters
12.4.1 The quantum asynchronous counter
12.4.2 The quantum synchronous counter
13 The quantum controlled ternary barrel shifter
13.1.1 The quantum ternary Peres gate
13.1.2 The quantum ternary modified Fredkin gate
13.2 Properties of ternary quantum circuits
13.3 The quantum barrel shifter
13.4 The design of a quantum ternary barrel shifter
13.4.1 The optimized quantum ternary barrel shifter
13.4.2 Properties of the designed circuit
14 Quantum random access memory
14.1 The quantum n-to-2n decoder
14.3 The construction procedure of the quantum RAM
15 The quantum arithmetic logic unit
15.1 The design of a quantum ALU
16 Applications of quantum computing technology
16.1.1 Roswell Park Cancer Institute
16.2.2 Los Alamos National Laboratory
16.8 Circuit, software, and system fault simulation
Part II Quantum fault tolerance
17 Quantum fault-tolerant circuits
17.1 The need for quantum fault-tolerant circuits
17.2 The fault-tolerant quantum adder
17.2.1 The fault-tolerant full-adder
17.3 The fault-tolerant multiplier
17.3.1 The fault-tolerant signed multiplier
17.4 The quantum fault-tolerant integer divider
17.4.1 The restoring division algorithm
17.4.3 The conditional addition operation module
17.4.4 Quantum restoring integer division circuitry
Part III Quantum-dot cellular automata
18 Quantum-dot cellular automata
18.1 Fundamentals of QCA circuits
18.3 Information and data propagation
18.4 Basic QCA elements and gates
18.5.1 Special cell arrangements and symmetric cells
18.5.3 Majority voter clock zones
19 QCA adder and subtractor
19.2 The QCA half-adder and half-subtractor
19.3 The QCA full-adder and full-subtractor
19.3.1 Implementation of the full-adder and full-subtractor
20 The QCA multiplier and divider
20.1.1 Multiplication networks
20.1.2 QCA multiplication networks
20.2.1 The non-restoring binary divider
21 QCA asynchronous and synchronous counters
21.1.1 The dual-edge triggered J-K flip-flop
21.1.2 The design of dual-edge triggered J-K flip-flop
21.1.3 The asynchronous backward counter
21.2.1 QCA synchronous counters
22 The QCA decoder and encoder
22.2.1 The QCA turbo encoder design
22.2.2 The RC encoder with single-feedback
22.2.3 The RC encoder with multi-feedback
23 The QCA multiplexer and demultiplexer
23.1 The QCA 2-to-1 multiplexer
23.2 The QCA 4-to-1 multiplexer
23.3 The QCA 1-to-2 demultiplexer
23.4 The QCA 1-to-4 demultiplexer
23.5 Multiplexing/demultiplexing using QCA
23.5.1 The effect of the selector line (S0,S1) on the 2-to-1 MUX/1-to-2 DEMUX
24 The QCA RAM, ROM, and processor
24.3.3 The arithmetic logic unit
