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1 Amerasekera, A. and Duvvury, C. (2002). ESD in Silicon Integrated Circuits, 2e. Wiley. ISBN: 0 470 49871 8.

2 Industry Council on ESD Target Levels (2010a) White paper 2: A case for lowering component level CDM ESD specifications and requirements. Rev. 2.0. http://www.esdindustrycouncil.org/ic/en/documents/6-white-paper-2-a-case-for-lowering-component-level-cdm-esd-specifications-and-requirements [Accessed: 10th May 2017]

3 Industry Council on ESD Target Levels (2010b) White paper 3: System Level ESD Part I: Common Misconceptions and Recommended Basic Approaches. Rev. 1.0 http://www.esdindustrycouncil.org/ic/en/documents/7-white-paper-3-system-level-esd-part-i-common-misconceptions-and-recommended-basic-approaches [Accessed: 10th May 2017]

4 Industry Council on ESD Target Levels (2011) White paper 1: A case for lowering component level HBM/MM ESD specifications and requirements. Rev. 3.0. Available from: http://www.esdindustrycouncil.org/ic/en/documents/37-white-paper-1-a-case-for-lowering-component-level-hbm-mm-esd-specifications-and-requirements-pdf [Accessed: 10th May 2017]

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7 Montrose, M. (2000). Printed Circuit Board Design Techniques for EMC Compliance, 2e. Wiley Interscience/IEEE Press. ISBN: 0 7803 5376 5.

8 Reliability Analysis Center (1979). Electrical Overstress/Electrostatic Discharge Symposium Proceedings. EOS‐1. Griffiss AFB, NY: Reliability Analysis Center.

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10 Smallwood J., Taminnen P., Viheriaekoski T. (2014) Paper 1B.1. Optimizing investment in ESD Control. In: Proc. EOS/ESD Symp. EOS‐36.

11 Wang, A.Z.H. (2002). On‐Chip ESD Protection for Integrated Circuits. Klewer Academic Press.

12 Welker, R.W., Nagarajan, R., and Newberg, C. (2006). Contamination and ESD Control in High‐Technology Manufacturing. Wiley‐Interscience/IEEE Press. ISBN‐10: 0 471 41452 2 ISBN‐13: 978 0 471 41452 0.

13 Williams, T. (2007). EMC for product designers, 4e. Newnes. ISBN‐13: 978‐0750681704 ISBN‐10: 0750681705.