Читать книгу Handbook of Microwave Component Measurements - Joel P. Dunsmore - Страница 112

Now, most modern VNAs incorporate a high‐speed ADC and perform direct sampling of the first IF signal. An example of a VNA digital‐IF block diagram is shown in Figure 2.23. The IF signal is preconditioned with adjustable gain to optimize the signal‐to‐noise ratio in the ADC. For some applications, it is useful to have a narrowband pre‐filter before the ADC so that the IF can be switched between a wideband IF and a narrowband response. An anti‐alias filter is used just before the ADC, with a bandwidth of about one‐third to one‐fourth that of the ADC clock rate.

Figure 2.23 Digital IF block diagram.

The FPGA that processes the ADC readings can be configured as a digital second converter of flexible IF frequency, so the final digital IF frequency can be quite arbitrary. There are several modes of operation for the digital IF. For these high‐speed ADCs, the raw ADC readings have very high bit rates. Some of the latest designs for VNAs have four channels of data, at 16 bits and 100 mega‐samples per second to produce a data rate of 6.4 Gbps. Specialized conditioning of the signal and advanced digital signal processing (much of which is proprietary) can improve the performance of the IF ADCs to many more effective bits.

At these high data rates, the main CPU cannot process the data fast enough to keep up, so an FPGA is used to decimate and filter the signals before the processed data is sent to the main processor using shared DMA memory. The function of decimation and filtering is the basic data processing step of any digital IF; in this function, a measurement is performed by setting the source and receiver frequencies so that the first IF contains the signal of interest. The ADC samples the IF signal, typically with two to four times over sampling, although it can be as much as 60 or 100 times over sampled. A finite set of samples is processed by the FPGA to produce a final result that represents the real and imaginary parts of the signal being measured. For example, if the digital IF is operating at 100 Msps, the IF frequency is 10 MHz, and the IF filter is set to 100 kHz IF BW, then approximately 10 μs of data are captured, or approximately 1000 data samples. These 1000 samples are processed by a multiply‐add chain in the FPGA to both filter the response and extract the real and imaginary values. In this way, the 1000 samples are reduced to two samples.

A second mode of operation for the digital IF is “ADC capture” mode. In this mode, the FPGA does not process the data; rather, the data samples are simply captured into the local memory in the digital IF for a finite period of time. The entire ADC data stream is available for any further processing that might be beyond the algorithms available in the FPGA. Some modern VNAs have memory depths up to 4 Gb allowing deep memory captures. This mode of operation, while not typical, is useful for capturing anomalous effects such as transient or pulsed responses, as well as more complicated functions such as de‐modulation of IF signals.