Читать книгу Multi-Processor System-on-Chip 2 - Liliana Andrade - Страница 22

We see that the 3GPP specifications follow the trend and vision of 5G laid out in section 1.2.1, incorporating the variability of workloads as the central paradigm.

With throughput requirements varying by several orders of magnitude, a homogeneous HW solution would be very inefficient for both high-end and low-end use cases. Rather, a heterogeneous HW architecture that is a mixture of HW accelerator engines, banks of programmable processing elements and supporting memory systems would be efficient. Accelerator engines such as dedicated (application-specific) HW accelerators and ASIPs are ideal to deal with extreme high-end use cases and easy-to-scale low-varying algorithms or processing steps, due to their speed and efficient energy per data point consumption. While banks of programmable processing elements such as vDSPs (SIMD cores with signal processing-oriented instruction set architecture) and generic scalar reduced instruction set computer (RISC) cores are ideal to deal with moderate–high to low-end use cases and processing steps that require flexibility, for example, choosing from a set which algorithm to perform, based on the device’s situational parameters and environmental conditions. Such HW is well suited for dealing with highly variable loads by powering HW modules on and off based on the current load. For example, if enough compute resources are available on the vDSPs, i.e. available idle cycles, we could run the communication kernels on the vDSPs in a time-multiplexed manner and keep the HW accelerators off.

Figure 1.5. Tiled “Kachel” MPSoC with decentralized tightly coupled memories

When it comes to MPSoC architecture in the sense of module arrangement and layout, we have recently published works with both decentralized (e.g. in Figure 1.5, (Fettweis et al. 2019)) and centralized (e.g. in Figure 1.6, (Damjancevic et al. 2019)) memory in mind. Although this chapter follows closely the later work, the programmable vector processor is a common processing element in both, and the lessons learned are universal¹³.

Figure 1.6. Heterogeneous MPSoC with a central shared memory architecture

Without discussing the layouts, as both have their advantages, let us delve into the common thread and analyze the combined effect of workloads and algorithms on HW provisioning requirements and possibly confirm our hypothesis that a heterogeneous MPSoC is required for an efficient future-proof solution.