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It is possible to combine the addressing modes above. Some processors offer indirect addressing with indexing. The associated terms “pre-indexing” and “post-indexing” will qualify at what step of the address calculation the indexing will apply. Pre-indexing means that indexing is carried out on the indirection address (pre-indexed indirect addressing mode), hence the second name, “indexed indirect addressing mode”.

We will have:

[1.8]

Figure 1.19 shows the mechanism. One example was MCS6502, which included two registers called “index registers X and Y” even though X has already served for indirection. Its designer calls this mode (indirect,X), which is justified by the relationship [1.8]. It was also suggested by MC6809. DEC used the term “index deferred addressing mode”.

Figure 1.19. Indirect indexed addressing or pre-indexing

Post-indexed indirect addressing mode or indirect indexed addressing mode applies indexing after indirection, as illustrated in Figure 1.20. We will have:

[1.9]

[1.10]

Figure 1.20. Indirect indexed addressing or post-indexing

The peculiarity of MCS6502 is that it used zero-page addressing as the address field was limited to 8 bits and the indexing occurred only on the lower part of the address (Figure 1.21). Its designer calls this mode (indirect),Y, which is justified by the relationship [1.10].

Figure 1.21. Indirect indexed zero-page addressing of MCS6502

A representative, penultimate example is MC6809, which offers 18 variations in mode, combining indexed and indirect addressings with the possibility of automatic post-increment or pre-decrement. This post-increment or pre-decrement is useful for managing a stack's pointer. Table 1.2 summarizes the possible combinations. R represents one of the four registers that can be used for indexing, the classics X and Y and the stack pointers user U and material S. Note the addressings using the program counter at the end. The offset is expressed in complement to 2ⁿ representation.

Indexed and based addressings with or without offset (based indexed plus displacement addressing mode) can be combined, thus offering, for example, 17 possible variations in the case of microprocessor x86. One example of this use is addressing an array of records, of a vector or of a structure, the base pointing the start of the array and index, an element of the array and the displacement, a field of the element.

Table 1.2. Combined MC6809 addressing modes

MC6809 assembly language notation	Description
,R	Zero-offset indexed
[,R]	Zero-offset indexed indirect
,R+	Zero-offset indexed post-increment of 1 (auto-increment R)
,R++	Zero-offset indexed post-increment of 2 (auto-increment R)
[,R++]	Zero-offset indexed post-increment of 2 indirect (auto-increment R)
,-R	Zero-offset indexed pre-decrement of 1 (auto-decrement R)
,--R	Zero-offset indexed pre-decrement of 2 (auto-decrement R)
[,--R]	Zero-offset indexed pre-decrement of 2 indirect (auto-decrement R)
n,R	Constant signed offset indexed (5, 8 or 16 bits offset from R)
[n,R]	Constant signed offset indexed indirect (5, 8 or 16 bits offset from R)
A,R	Accumulator A signed offset from R indexed
[A,R]	Accumulator A signed offset from R indexed indirect
B,R	Accumulator B signed offset from R indexed
[B,R]	Accumulator B signed offset from R indexed indirect
D,R	Accumulator D signed offset from R indexed
[D,R]	Accumulator D signed offset from R indexed indirect
n,PCR	Constant signed offset from PC indexed (8 or 16 bits)
[n,PCR]	Constant signed offset from PC indexed indirect (8 or 16 bits offset)
[n]	Extended indirect