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1 Chapter 1Figure 1.1. Breakdown of an instructionFigure 1.2. An example of the structure of an operation codeFigure 1.3. Format of an instruction with two operandsFigure 1.4. An instruction with several operandsFigure 1.5. Three fixed formats for MIPS instructionsFigure 1.6. Typical instruction format from 8086/88Figure 1.7. Variable instruction format Intel IA-32 and Intel 64 (Intel 2016) ar...Figure 1.8. Instruction with an operand fieldFigure 1.9. Execution of an instruction using register addressing from one regis...Figure 1.10. Instruction with direct addressingFigure 1.11. Instruction with an address at page 0Figure 1.12. Execution of an instruction in relative addressingFigure 1.13. Seeking an operand in relative addressingFigure 1.14. Instruction with indirect register addressingFigure 1.15. Instruction with indirect memory addressingFigure 1.16. Execution of an instruction in indexed addressing with displacement...Figure 1.17. Execution of an instruction in indexed addressing with displacement...Figure 1.18. Execution of an instruction in base addressing with displacementFigure 1.19. Indirect indexed addressing or pre-indexingFigure 1.20. Indirect indexed addressing or post-indexingFigure 1.21. Indirect indexed zero-page addressing of MCS6502Figure 1.22. Execution of an instruction in bit addressingFigure 1.23. Window of five samplesFigure 1.24. Circular bufferFigure 1.25. Comparison between linear and circular addressings (from Rao (2001)...Figure 1.26. Flow diagram of the algorithm of an 8-point FFT DIT in base 2

2 Chapter 2Figure 2.1a. Instruction classification in modern MPUsFigure 2.1b. Classifying instructions in modern MPUs (continuation and end)Figure 2.2a. Classification of the main bit manipulation operationsFigure 2.2b. Classification of the main bit manipulation operations (continuatio...Figure 2.3. Logical left and right shiftsFigure 2.4. Shift arithmetic rightFigure 2.5. Left and right rotationsFigure 2.6. Left and right rotations through carryFigure 2.7. Generic examples of multiple shifts and rotationFigure 2.8. Double shift with a 386Figure 2.9. Field extract and field deposit operationsFigure 2.10. Left shuffle operation (interleaving)Figure 2.11. Right shuffle operation (interleaving)Figure 2.12. Reverse instructions from the Arm® and Thumb® family (n = 64)Figure 2.13. Classifying advanced bit manipulationsFigure 2.14. Field extract and field deposit operations of parallel bitsFigure 2.15. Normal butterfly circuit in n = 8 bits format (a) and associated sw...Figure 2.16. Reverse butterfly circuit in n = 8 bits formatFigure 2.17. Branching instructionsFigure 2.18. Execution paths for a jumpFigure 2.19. Execution steps for a conditional jumpFigure 2.20. Execution paths for a conditional jumpFigure 2.21. Left: result state check; right: direct checkFigure 2.22. Schema for evaluating a calculationFigure 2.23. Condition field from MPU Arm® VL86C010Figure 2.24. Instruction bufferFigure 2.25. Hardware management of a loopFigure 2.26. Functional block diagram showing a hardware loop manager (from Tsao...Figure 2.27. Distribution of operations in a vector instruction in a SIMD struct...

3 Chapter 3Figure 3.1. Instruction alignment in 32-bit format (from Darche (2012) modified)Figure 3.2. Levels of programming languageFigure 3.3. Hierarchy of protected execution modes from the x86 family from Inte...Figure 3.4. Operating modes of an MPU from IA-323 architecture from Intel® (Inte...Figure 3.5. Virtualization in an applicationFigure 3.6. Hypervision of virtual machinesFigure 3.7. Differences between container (a) and serverless (b) (from Wong (201...Figure 3.8. Hierarchization of the instruction set from x86 architectureFigure 3.9. Backward compatibility of the instruction set architecture by enrich...Figure 3.10. Types of compatibility of a digital systemFigure 3.11. Evolution of the calculating performance (MIPS) of the first MPUs f...Figure 3.12. Development of MPU systems’ performance over time (SPECint)Figure 3.13. Comparison of uniprocessor performances between supercomputers and ...Figure 3.14. Comparing (single-core) MPU performances with DRAM8 performances (f...Figure 3.15. Comparison of performances between computer classes (from Hennessy ...

4 Chapter 4Figure 4.1. Suggested visual representation of a stack SFigure 4.2. Pseudo-code for stacking (a) and unstacking (b) in the format n = 16...Figure 4.3. Operations of stacking and unstacking for TMS320C31Figure 4.4. Managing an ascending stackFigure 4.5. Classical structure of an execution stack (x86 family from Intel)Figure 4.6. Classic main memory mappingFigure 4.7. Stack register of a mathematical coprocessor in floating point from ...Figure 4.8. Stack in shift-register versionFigure 4.9. Unfolding execution of a program with a call to sub-programFigure 4.10. Subroutine call and return and stack content (x86 architecture)Figure 4.11. Recursive calls and returns from a subroutine (nested calls)Figure 4.12. Recursive calls and returns from a subroutine (nested calls)Figure 4.13. Windowing registers (from Scott (2016))

5 Chapter 5Figure 5.1. Origins of an interrupt request (Darche 2003)Figure 5.2. Ideal forms of external interrupt requestFigure 5.3. Call and return of a non-nested hardware interruptFigure 5.4. Execution flow of a program during a hardware interrupt requestFigure 5.5. Stages in handling an interruptFigure 5.6. Different sources of external interruptsFigure 5.7. Example of management logic for IT requests (Meinadier 1971, 1988)Figure 5.8. Processing chain for several sources of interrupt sharing a single i...Figure 5.9. Simplified decision organigram for considering a hardware interruptFigure 5.10. Execution organigram of a simple MPU: the MC6802 (Motorola 1984)Figure 5.11. Pre-emptive execution in a system of hierarchized interruptsFigure 5.12. Simplified processing logigram of an interrupt from the IT 8259A co...Figure 5.13. Mechanism of nested hardware interruptsFigure 5.14. Call and return of a non-nested software interrupt (example with MC...Figure 5.15. Call and return of nested software interrupts (example with MC6809)Figure 5.16. Call and return of nested software interrupts (example with MC6809)Figure 5.17. Decision process from MC6809 (simplified organigram without HALT an...Figure 5.18. Processing sequence for interrupt requests from 8086 (Intel 1989)Figure 5.19. Step-by-step execution modes with NMI and normal (Intel 1989)Figure 5.20. Simultaneous software exception and maskable external interrupt int...Figure 5.21. Simultaneous NMI, INTR and division by zero in interaction with ste...Figure 5.22. Processing organigram for interrupts from MC6809 (Motorola 1981, 19...Figure 5.23. Vectorization of the interruptFigure 5.24. External vectorizationFigure 5.25. Two typical implantations of different memory areas of an IT systemFigure 5.26. Proposal for processing flow for many IT requests (Intel 1980)Figure 5.27. Organization of different APICs

6 ExercisesFigure E2.28. Generation of address signals corresponding to an execution of a s...