Читать книгу Microprocessor 4 - Philippe Darche - Страница 4

1 Chapter 1Table 1.1. Possible address combinations in family IA-32Table 1.2. Combined MC6809 addressing modes

2 Chapter 2Table 2.1. Logical instructions from DEC System-10Table 2.2. Conditional jump instructions for 8086 for whole numbersTable 2.3. Condition codes from the Arm® architecture

3 Chapter 3Table 3.1. Additional cost in the number of cycles and memory clutter for the MC...Table 3.2. Effective address calculation time (8086)Table 3.3. Arm® architecture execution modesTable 3.4. List of iCOMP benchmarks

4 Chapter 4Table 4.1. Solutions for managing a stack in main memory

5 Chapter 5Table 5.1. Maskable and non-maskable interruptsTable 5.2. Categories of interrupt to qualify a double fault in 80386 (Intel 198...Table 5.3. Decision criteria for qualifying a double fault in 80386 (Intel 1986)Table 5.4. Priorities of different interrupts from 8086Table 5.5. Table of 256 interrupt vectors from IA-32 architectureTable 5.6. List of exception codes (ExcCode) for MIPS architecture (Kane 1988; K...Table 5.7. Management options in the case of multiple IT processingTable 5.8. Table summarizing interruptsTable 5.9. Interrupt recovery points for the 80286Table 5.10. Recovery point for ITs for the 80286 (real mode)Table 5.11. Recovery point for ITs for the 80286 (protected mode)Table 5.12a. Suggestion for classification criteria according to Hennessy and Pa...Table 5.12b. Suggestion of classification criteria according to Hennessy and Pat...

6 AppendixTable A.1a. Hexadecimal values of machine codesTable A.1b. Hexadecimal values of machine codesTable A.2a. Programming aidTable A.2b. Programming aidTable A.2c. Programming aid