Читать книгу Digital VLSI Design and Simulation with Verilog - Suman Lata Tripathi - Страница 5

1 Chapter 1Figure 1.1 Symbol of an AND gate.Figure 1.2 Symbol for an OR gate.Figure 1.3 Symbol for a NOT gate.Figure 1.4 Symbol for a NAND gate.Figure 1.5 Symbol for a NOR gate.Figure 1.6 Symbol for a NAND gate.Figure 1.7 Diagram of a combinational logic circuit.Figure 1.8 Block diagram of a H. adder.Figure 1.9 Circuit diagram of a half adder.Figure 1.10 Block diagram of a full adder.Figure 1.11 Full adder logic block.Figure 1.12 Half subtractor.Figure 1.13 Half subtractor logic block.Figure 1.14 Block diagram of the full subtractor.Figure 1.15 Full subtractor logic block.Figure 1.16 Block diagram of the multiplexer.Figure 1.17 Logic diagram of the multiplexer.Figure 1.18 Implementation of function.Figure 1.19 Block diagram of the de-multiplexer.Figure 1.20 1 × 4 de-multiplexer using logic gates.Figure 1.21 Block diagram of a 2 × 4 decoder.Figure 1.22 Logic diagram of a 2 × 4 decoder.Figure 1.23 Implementation of functions using the decoder.Figure 1.24 Block diagram of a 2-bit binary multiplier.Figure 1.25 Circuit diagram of a 2-bit multiplier.Figure 1.26 2-bit comparator block.

2 Chapter 2Figure 2.1 Clocked S-R F/F.Figure 2.2 Clocked D-F/F.Figure 2.3 Clocked J-K F/F.Figure 2.4 Master-slave of a J-K F/F.Figure 2.5 Clocked T-F/F.Figure 2.6 Excitation table of a) S-R, b) D, c) J-K and d) D- F/F.Figure 2.7 Characteristic table a) D-F/F and b) T-F/F.Figure 2.8 SISO shift register block diagram.Figure 2.9 SIPO shift register block diagram.Figure 2.10 PIPO shift register block diagram.Figure 2.11 PISO shift register block diagram.Figure 2.12 3-bit Synchronous up-counter with J-K F/F.Figure 2.13 3-bit ripple counter (up-counter).Figure 2.14 State diagram of a 3-bit up-counter.Figure 2.15 3-bit up-counter logic block.Figure 2.16 4-bit ring counter using D-F/F.Figure 2.17 4-bit Johnson counter using D-F/F.Figure 2.18 Mealy machine.Figure 2.19 Moore machine.Figure 2.20 Design 011 sequence using a Mealy machine.Figure 2.21 State-diagram representation of Moore model.Figure 2.22 Sequence circuit of 011 Mealy sequences.

3 Chapter 3Figure 3.1 Top-down design methodology.Figure 3.2 Bottom-up design methodology.Figure 3.3 Design flow chart.

4 Chapter 4Figure 4.1 Logic circuit.Figure 4.2 Logic circuit.Figure 4.3 Block diagram of a half adder.Figure 4.4 Logic circuit of half adder.Figure 4.5 Logic circuit of half adder using a NAND gate.Figure 4.6 Logic circuit of half adder using NOR gate.Figure 4.7 Block diagram of a full adder.Figure 4.8 Logic circuit of a full adder.Figure 4.9 Block diagram of a half subtractor.Figure 4.10 Logic circuit of a full subtractor.Figure 4.11 Logic circuit of a half subtractor using a NAND gate.Figure 4.12 Logic circuit of the half subtractor using a NOR gate.Figure 4.13 Block diagram of a full subtractor.Figure 4.14 Logic circuit of a full subtractor.Figure 4.15 Block diagram of a 2 × 1 multiplexer.Figure 4.16 Logic circuit of a 2 × 1 multiplexer.Figure 4.17 Block diagram of a 4 × 1 multiplexer.Figure 4.18 Logic circuit of a 4 × 1 multiplexer.Figure 4.19 Block diagram of 1 × 2 de-multiplexer.Figure 4.20 Logic circuit of a 1 × 2 de-multiplexer.Figure 4.21 Block diagram of 2-to-4 decoder.Figure 4.22 Logic circuit of a 2-to-4 decoder.Figure 4.23 Block diagram of 4-to-2 encoder.Figure 4.24 Logic circuit of 4-to-2 encoder.Figure 4.25 Logic circuit of a 1-bit magnitude comparator.

5 Chapter 5Figure 5.1 Block diagram of 2 × 1 multiplexer.Figure 5.2 Block diagram of 4 × 1 multiplexer.

6 Chapter 6Figure 6.1 Logic circuit of a full adder [1].Figure 6.2 Block diagram of a 4-bit full adder [1].Figure 6.3 Logic circuit of 4 × 1 multiplexer.Figure 6.4 Block diagram of a 2-to-4 decoder.Figure 6.5 Block diagram of a 4-to-2 decoder.Figure 6.6 Block diagram of the D-Latch.Figure 6.7 Block diagram of a D-F/F.Figure 6.8 Block diagram of the J-K F/F.Figure 6.9 Block diagram of the D-F/F using J-K F/F.Figure 6.10 Block diagram of the J-K F/F using T-F/F.Figure 6.11 Block diagram of an S-R F/F using J-K F/F.

7 Chapter 7Figure 7.1 CMOS design with pull-up and pull-down network.Figure 7.3 MOS switches (a) NMOS (b) PMOS.Figure 7.4 Symbol of a CMOS switch.Figure 7.5 Resistive Switches (a) tran (b) tranif1 (c) tranif0.Figure 7.2 CMOS inverter.Figure 7.6 NAND gate implantation at transistor level.Figure 7.7 AND gate using MOS switches.Figure 7.8 NOR gate using switches.Figure 7.9 OR gate using switches.Figure 7.10 XOR gate using switch.Figure 7.11 2 × 1 Multiplexer block.Figure 7.12 2 × 1 Multiplexer using a CMOS switch.Figure 7.13 4 × 1-multiplexer block.Figure 7.14 4 × 1-multiplexer using switches.Figure 7.15 1-bit full-adder implementation using a 4 × 1 multiplexer.

8 Chapter 8Figure 8.1 A simple combinational circuit indicating distributed delay.Figure 8.2 A simple combinational circuit indicating lumped delay.Figure 8.3 Possible path from individual input to output.

9 Chapter 9Figure 9.1 VLSI design flow at RTL level.Figure 9.2 Example of function implementation with PROM.Figure 9.3 Example of function implementation with PAL.Figure 9.4 Example of function implementation PLA.Figure 9.5 CPLD block diagram.Figure 9.6 PAL-macrocellFigure 9.7 FPGA block diagram.Figure 9.8 2-Input LUT.Figure 9.9 3-Input LUT.Figure 9.10 Digital design flow.

10 Chapter 10Figure 10.1 New project creation on Xilinx ISE simulator.Figure 10.2 New source module creation on Xilinx.Figure 10.3 Xilinx platform for Verilog HDL.Figure 10.4 Behavioral simulation on Xilinx platform.Figure 10.5 4-bit ripple-carry full adder.Figure 10.6 4-bit CLA adder.Figure 10.7 4-bit CSA block diagram.Figure 10.8 Truth table and K-map.Figure 10.9 1.8: 4 × 16 decoder using a 2 × 4 decoder.Figure 10.10 8-bit LFSR.

11 Chapter 1Table 1.1 T. Table of AND gate.Table 1.2 Truth table of an OR gate.Table 1.3 Truth table of a NOT gate.Table 1.4 Truth table of a NAND gate.Table 1.5 Truth table of a NOR gate.Table 1.6 Truth table of a NAND gate.Table 1.7 Truth table of a half adder.Table 1.8 Truth table of a full adder.Table 1.9 Truth table of the H. subtractor.Table 1.10 Truth table of the full subtractor.Table 1.11 Truth table of the Table 1.12 Truth table of a 1 × 4 de-multiplexer.Table 1.13 Truth table of decoder 2 × 4.Table 1.14 Truth table of a 2-bit comparator.Table 1.15 Octal to Binary converter.Table 1.16 Truth table of a decimal to BCD encoder.

12 Chapter 2Table 2.1 Truth table of an S-R F/F.Table 2.2 Truth table of a D-F/F.Table 2.3 Truth table of a J-K F/F.Table 2.4 Truth table of a T-F/F.Table 2.5 State diagram of a 3-bit counter.Table 2.6 Excitation table of a T-F/F.Table 2.7 State table of a 3-bit counter.Table 2.8 D-F/F excitation table.Table 2.9 State table 1 of sequence 011.Table 2.10 State table 2 of sequence 011.

13 Chapter 4Table 4.1 Half adder.Table 4.2 Full adder.Table 4.3 Half subtractor.Table 4.4 Full subtractor.Table 4.5 2 × 1 multiplexer.Table 4.6 4 × 1 multiplexer.Table 4.7 1 × 2 de-multiplexer.Table 4.8 2-to-4 decoderTable 4.9 4-to-2 encoder.Table 4.10 1-bit magnitude comparator.

14 Chapter 5Table 5.1 Half adder.Table 5.2 Half subtractor.Table 5.4 4 × 1 multiplexer.Table 5.3 2 × 1 multiplexer.Table 5.5 2 × 1 multiplexer.Table 5.6 4 × 1 multiplexer.Table 5.7 2-to-4 decoder.Table 5.8 1-bit magnitude comparator.

15 Chapter 6Table 6.1 Half adder.Table 6.2 Full adder.Table 6.3 2 × 1 multiplexer.Table 6.4 4 × 1 multiplexer.Table 6.5 2-to-4 decoder.Table 6.6 Decoder truth table.Table 6.7 D-F/F truth table.Table 6.8 J-K F/F.

16 Chapter 7Table 7.1 Truth table of a NAND gate.Table 7.2 Truth table of an AND gate.Table 7.3 Truth table of a NOR gate.Table 7.4 Truth table of an OR gate.Table 7.5 Truth table of an XOR gate.Table 7.6 Truth table of an OR gate.Table 7.7 Truth table of a 4 × 1 multiplexer.

17 Chapter 8Table 8.1Table 8.2 Differences between task and function.

18 Chapter 9Table 9.1 Examples of function implementation using a 2-input LUT.Table 9.2 Xilinx FPGA family.