Читать книгу Origin of Power Converters - Tsai-Fu Wu - Страница 4

1 Chapter 1Figure 1.1 Configuration of a power processing system.Figure 1.2 Block diagram of a linear regulator.Figure 1.3 Block diagram of a switching regulator.Figure 1.4 Possible components in a power converter.Figure 1.5 (a) Capacitor–capacitor–switch, (b) inductor–inductor–switch, and...Figure 1.6 Non‐PWM converters: (a) two lift, (b) KY, and (c) re‐lift circuit...Figure 1.7 Power converters with a second‐order LC network and a pair of act...Figure 1.8 Power converters with a fourth‐order LC network and a pair of act...Figure 1.9 Converters with a fourth‐order network: (a) buck derived, (b) boo...Figure 1.10 Converters with a switched inductor/capacitor: (a) buck derived,...Figure 1.11 (a) Voltage‐fed, (b) current‐fed, and (c) quasi‐Z‐source convert...Figure 1.12 Quasi‐resonant converters: (a) buck type, (b) boost type, and (c...Figure 1.13 Converters with multiple pairs of active–passive switches: (a) h...Figure 1.14 Isolated PWM converters: (a) flyback, (b) forward, (c) push‐pull...Figure 1.15 PWM converters with coupled inductors: (a) buck type, (b) boost ...Figure 1.16 (a) P cell and (b) N cell.Figure 1.17 (a) Tee canonical cell and (b) Pi canonical cell.Figure 1.18 (a) Buck and inverse buck and (b) boost and inverse boost.Figure 1.19 With the same input‐to‐output transfer ratio of (2D − 1)/(1 − D)...Figure 1.20 (a) Switched‐capacitor and (b) switched‐inductor cells.Figure 1.21 Structure of PWM converters used in the derivation procedure.Figure 1.22 Possible positions of the inductor in a second‐order PWM convert...Figure 1.23 Evolution of the buck‐boost converter from the buck and boost co...Figure 1.24 Four types of grafted switches: (a) T‐type, (b) inverse T‐type, ...Figure 1.25 Illustration of the buck‐boost converter derived with the graft ...Figure 1.26 Derivation of the buck‐boost converter with the converter layer ...

2 Chapter 2Figure 2.1 Derivation of the original converter, buck converter, with a sour...Figure 2.2 Analogy of the buck converter derivation to proton–neutron–meson ...Figure 2.3 Three types of configurations of power transfer between capacitor...Figure 2.4 Practical examples applying the configuration shown in Figure 2.3...Figure 2.5 (a) The buck converter, (b) inductor voltage V_L1 and current i_L1,...Figure 2.6 Decoding, synthesizing, and evolution of buck‐boost and boost con...Figure 2.7 (a) Inverse buck, (b) inverse boost, and (c) inverse buck‐boost w...Figure 2.8 Dual RLC networks (a) in series and driven by a voltage source an...Figure 2.9 Topologically dual converters: (a) buck and (b) boost.Figure 2.10 Component realization of (a) buck and (b) boost converters.

3 Chapter 3Figure 3.1 (a) Circuit configuration of power transfer between capacitor and...Figure 3.2 A voltage source in series with a capacitor is equivalent to a si...Figure 3.3 Illustration of capacitor C₁ with different DC offset voltages in...Figure 3.4 Buck converter applying DC voltage offsetting to yield different ...Figure 3.5 Buck and its equivalent configurations with C_f –L_f fi...Figure 3.6 Equivalent converters derived from Ćuk converter.Figure 3.7 A current source in parallel with an inductor is equivalent to a ...Figure 3.8 Illustration of inductor L₁ with different DC offset currents in ...Figure 3.9 Boost converter with different DC voltage offset configurations....Figure 3.10 The input of the boost converter represented in current form.Figure 3.11 A capacitor is split into (a) two and (b) three capacitors with ...Figure 3.12 Illustration of invalid capacitor splitting. (a) a capacitor is ...Figure 3.13 An inductor is split into two inductors (a) and (b) with identic...Figure 3.14 Two typical configurations for generating pulsating voltages. (a...Figure 3.15 (a) Smooth voltage obtained from the pulsating voltage across di...Figure 3.16 (a) Smooth output voltage V_o obtained with a filter capacitor, (...Figure 3.17 (a) Buck converter with a secondary winding coupled from the ind...Figure 3.18 The secondary (a) with two forward‐type rectifications, (b) with...Figure 3.19 Boost converter with (a) a secondary winding coupled from the in...Figure 3.20 DC transformers with (a) push‐pull type, (b) full‐bridge type, a...Figure 3.21 (a) Full‐bridge diode rectifier, terminal outputs with (b) type‐...Figure 3.22 (a) Buck converter partitioned in five positions, (b) a DC trans...Figure 3.23 (a) Buck and boost converters in cascade, (b) relocating switch Figure 3.24 (a) Switches with a common node s–s, (b) T‐type grafted switch (...Figure 3.25 (a) Boost and buck converters in cascade connection, (b) relocat...Figure 3.26 Degeneration of TGS and ΠGS bidirectional current switches under...Figure 3.27 Degeneration of ITGS and IΠGS bidirectional current switches und...Figure 3.28 (a) Two diodes with common node N, (b) N‐type grafted diode (NGD...Figure 3.29 (a) Two diodes with common node P, (b) P‐type grafted diode (PGD...Figure 3.30 (a) Boost and buck converters in cascade connection with S₂ in t...Figure 3.31 (a) Buck converter, (b) input‐to‐output voltage transfer ratio i...Figure 3.32 (a) Boost converter with split output capacitor C_o, (b) input‐to...

4 Chapter 4Figure 4.1 Conceptual block diagram of power transfer from input (V_i, I_i) to...Figure 4.2 Gain‐D plots of step‐down transfer codes D and D².Figure 4.3 Gain‐D plots of step‐up transfer codes 1/(1 − D) and 1/(1 −...Figure 4.4 Gain‐D plots of step‐up/down transfer ratios D/(1 − D) and Figure 4.5 Gain‐D plots of ±step‐up/step‐down transfer codes (1 − D)/(...Figure 4.6 Transfer codes in a cascade configuration.Figure 4.7 Feedback configuration with a forward code TC_f and a feedback cod...Figure 4.8 Two examples to illustrate the feedback configuration: (a) forwar...Figure 4.9 Feedforward configuration: (a) a unity‐gain feedforward with a fo...Figure 4.10 Two examples to illustrate the feedforward configuration: (a) a ...Figure 4.11 Three combinational code configurations: (a) forward, feedback a...Figure 4.12 Parallel configuration of n transfer codes.Figure 4.13 Two possible configurations of D/(1 − 2D): (a) feedback configur...Figure 4.14 The two configurations shown in Figure 4.13 combined with a unit...Figure 4.15 (a) feedback configuration of transfer code: (−D)/(1 + 2D), and ...Figure 4.16 Conceptual power transfer through resonant converters, which can...Figure 4.17 Code configurations of transfer codes with multivariables: (a) c...Figure 4.18 Parallel configuration.Figure 4.19 Decoding with component‐interconnected expression: (a) buck and ...

5 Chapter 5Figure 5.1 (a) Buck converter, (b) boost converter, (c) buck–boost converter...Figure 5.2 (a) P‐cell and (b) N‐cell.Figure 5.3 (a) Buck converter synthesized with a P‐cell and (b) boost conver...Figure 5.4 (a) Sepic converter and (b) Zeta converter.Figure 5.5 (a) Sepic converter synthesized with an N‐cell and an LC filter a...Figure 5.6 (a) Tee canonical cell and (b) Pi canonical cell.Figure 5.7 (a) Buck and inverse buck and (b) boost and inverse boost.Figure 5.8 With the same input‐to‐output transfer ratio of (2D − 1)/(1 − D) ...Figure 5.9 (a) Switched‐capacitor and (b) switched‐inductor cells.Figure 5.10 Structure of PWM converters in the derivation procedure.Figure 5.11 Possible positions of the inductor in a second‐order PWM convert...Figure 5.12 Evolution of buck–boost converter with synchronous switches.Figure 5.13 Evolution of boost–buck (Ćuk) converter with synchronous switche...Figure 5.14 (a) Block diagram of two converters connected in series and (b) ...Figure 5.15 (a) Switches with common S–S, (b) TGS, (c) switches with common Figure 5.16 (a) Switches with common D–S, (b) ΠGS, (c) switches with common Figure 5.17 A MOSFET with its body diode to function as a bidirectional swit...Figure 5.18 Bidirectional grafted switches: (a) TGS, (b) ITGS, (c) ΠGS, and ...Figure 5.19 (a) Two diodes sharing a common node N, (b) grafted diode, and d...Figure 5.20 (a) Two diodes sharing a common node P, (b) grafted diode, and d...Figure 5.21 Processes of grafting a boost converter on a buck converter to y...Figure 5.22 Processes of grafting a buck converter on a boost converter to y...Figure 5.23 Processes of grafting a buck converter on a buck–boost converter...Figure 5.24 Processes of grafting a boost converter on a boost–buck converte...Figure 5.25 Processes of grafting a Zeta converter on a complementary buck c...Figure 5.26 Processes of synthesizing a buck converter and a buck–boost conv...Figure 5.27 Processes of grafting a buck converter on the other buck convert...Figure 5.28 Processes of grafting one boost converter on the other boost con...Figure 5.29 Processes of grafting a boost converter in CCM on a buck convert...Figure 5.30 Integration processes of cascode complementary Zeta converter wi...Figure 5.31 Process of grafting half‐bridge inverter on dither boost convert...Figure 5.32 Processes of grafting a half‐bridge resonant inverter on a bidir...Figure 5.33 Processes of grafting a class‐E converter on a boost converter t...Figure 5.34 Processes of grafting a buck converter on a boost converter to y...Figure 5.35 Processes of grafting a half‐bridge inverter on two interleaved ...Figure 5.36 Processes of grafting N‐converters with a TGS.Figure 5.37 Processes of grafting N‐converters with a ΠGS.

6 Chapter 6Figure 6.1 (a) Illustration of a layer scheme in three steps and (b) concept...Figure 6.2 Derivation of the buck–boost converter with the converter layerin...Figure 6.3 Illustration of Zeta converter synthesis with a buck converter an...Figure 6.4 Universal converter configuration of the buck family.Figure 6.5 Two additional converter topologies derived from the universal fo...Figure 6.6 Illustration of the boost family synthesized with the layer schem...Figure 6.7 Universal form of the boost family.Figure 6.8 Two additional converter topologies derived from the universal fo...Figure 6.9 Zeta converter with a positive unity feedback and the layer schem...Figure 6.10 Sepic converter with a positive unity feedback and the layer sch...Figure 6.11 The converter depicted in Figure 6.9c with a negative unity feed...Figure 6.12 The converter depicted in Figure 6.10c with a negative unity fee...Figure 6.13 Illustration of a boost converter with a positive unity voltage ...Figure 6.14 Illustration of Ćuk converter with a negative unity voltage feed...Figure 6.15 Illustration of a buck–boost converter with a negative unity vol...Figure 6.16 Illustration of the deduction from the Ćuk converter to the buck...Figure 6.17 Illustration of the deduction from the sepic converter to the bu...Figure 6.18 Illustration of the deduction from the Zeta converter to the buc...Figure 6.19 Illustration of the deduction from the sepic converter to the Ze...Figure 6.20 Taking output from the other port of the Zeta converter to illus...

7 Chapter 7Figure 7.1 Code configuration for synthesizing the buck converter.Figure 7.2 Buck converter synthesized with the buck–boost converter and a ne...Figure 7.3 Buck converter synthesized with the Ćuk converter and a negative ...Figure 7.4 Two possible configurations of D/(1 − 2D): (a) feedback configura...Figure 7.5 The two configurations shown in Figure 7.4 combined with a unity‐...Figure 7.6 Illustration of synthesizing voltage‐fed z‐source converter with ...Figure 7.7 Illustration of synthesizing voltage‐fed z‐source converter with ...Figure 7.8 Illustration of synthesizing voltage‐fed z‐source converter with ...Figure 7.9 Code configuration of the current‐fed z‐source converter.Figure 7.10 Illustration of synthesizing the current‐fed z‐source converter ...Figure 7.11 Illustration of synthesizing the current‐fed z‐source converter ...Figure 7.12 Code configuration of the quasi‐z‐source converter.Figure 7.13 Illustration of synthesizing the quasi‐z‐source converter with a...Figure 7.14 Illustration of synthesizing the quasi‐z‐source converter with a...Figure 7.15 Three inverse converters including (a) I‐buck, (b) I‐boost, and ...Figure 7.16 Code configurations of the high step‐down transfer code D/(2 − DFigure 7.17 Illustration of synthesizing the high step‐down converter with a...Figure 7.18 Alternate code configurations of the high step‐down transfer cod...Figure 7.19 Illustration of synthesizing the high step‐down converter with a...Figure 7.20 Other code configurations for achieving the transfer code D/(2 −...Figure 7.21 A code configuration to realize the expression shown in Eq. (7.2...Figure 7.22 Illustration of synthesizing the high step‐down converter with a...Figure 7.23 Illustration of synthesizing the high step‐down converter with a...Figure 7.24 Illustration of a sepic converter as a forward path and an I‐buc...Figure 7.25 Illustration of a Zeta converter as a forward path and an I‐Ćuk ...Figure 7.26 Illustration of synthesizing the high step‐up converter with a b...Figure 7.27 Illustration of synthesizing the high step‐up converter with a Ć...Figure 7.28 Illustration of synthesizing the high step‐up converter with a Z...Figure 7.29 Illustration of synthesizing the high step‐up converter with a b...Figure 7.30 Illustration of synthesizing the high step‐up converter with a s...Figure 7.31 A code configuration of the transfer code D/(1 − 2D).Figure 7.32 Illustration of synthesizing the code configuration shown in Fig...Figure 7.33 Illustration of synthesizing the code configuration shown in Fig...Figure 7.34 Cascade code configuration of transfer code D²/(D² − 3D + 2).Figure 7.35 Illustration of synthesizing the code configuration shown in Fig...Figure 7.36 Illustration of synthesizing the code configuration shown in Fig...Figure 7.37 Illustration of synthesizing the code configuration shown in Fig...Figure 7.38 Zeta converter topology.Figure 7.39 Illustration of the Zeta converter with a DC voltage offsetting....Figure 7.40 Illustration of the Zeta converter with a DC voltage blocking an...Figure 7.41 Illustration of the Zeta converter with a magnetic coupling.Figure 7.42 Illustration of the Zeta converter with a DC transformer.Figure 7.43 Illustration of the Zeta converter with the layer technique and ...Figure 7.44 Illustration of the Zeta converter with the layer technique and ...Figure 7.45 Illustration of the Zeta converter with the layer technique and ...

8 Chapter 8Figure 8.1 Variations of the original converter: (a) a general type, (b) DC ...Figure 8.2 Syntheses of single‐phase converters: (a) combined two DC sources...Figure 8.3 Syntheses of other single‐phase converters: (a) combined two DC s...Figure 8.4 Syntheses of three‐phase converters: (a) full‐bridge three‐phase ...Figure 8.5 Synthesis of Vienna rectifier: (a) single phase and (b) three pha...Figure 8.6 A bidirectional switch realized with (a) two active switches, (b)...Figure 8.7 Configurations of (a) an MMC, (b) a half‐bridge cell, and (c) a f...Figure 8.8 Configurations of (a) a full‐bridge three‐level FCC for generatin...Figure 8.9 Full‐bridge resonant converters with (a) LC, (b) LCL, and (c) LLC

9 Chapter 9Figure 9.1 Illustration of a zero‐current switching.Figure 9.2 Proper locations of snubber inductor L₁ for PWM converters to ach...Figure 9.3 NZCS lossless cells with energy recovery: (a) associated with the...Figure 9.4 Passive soft‐switching buck converter with NZCS, in which the sof...Figure 9.5 Passive soft‐switching boost converter with NZCS, in which the so...Figure 9.6 Illustration of a zero‐voltage switching.Figure 9.7 Proper locations of snubber capacitor C₁ for PWM converters to ac...Figure 9.8 Near‐zero‐voltage turn‐off lossless snubbers with energy recovery...Figure 9.9 Passive soft‐switching buck converter with NZCS and NZVS.Figure 9.10 Passive soft‐switching boost converter with NZCS and NZVS.Figure 9.11 Zero‐voltage turn‐on lossless snubbers with energy recovery.Figure 9.12 Active soft‐switching converter with ZVS (type 1).Figure 9.13 Active soft‐switching converter with ZVS (type 2).Figure 9.14 Active soft‐switching converter with ZVS (type 3).Figure 9.15 Zero‐current turn‐off lossless snubber with energy recovery.Figure 9.16 Active soft‐switching converter with ZCS (type1).Figure 9.17 Active soft‐switching converter with ZCS (type2).Figure 9.18 Passive NZVS/NZCS soft‐switching buck and boost PWM converters: ...Figure 9.19 Derivation of the passive soft‐switching PWM buck–boost PWM conv...Figure 9.20 Derivation of the active soft‐switching PWM buck–boost SSC with ...Figure 9.21 Passive soft‐switching PWM DC/DC converters derived from the six...Figure 9.22 Illustration of buck–boost and Zeta passive soft‐switching conve...Figure 9.23 Illustration of Ćuk and sepic passive soft‐switching converters ...Figure 9.24 General configuration of a soft‐switching BCU with a feedback ne...Figure 9.25 Two derived passive soft‐switching converters from the general c...Figure 9.26 A list of active soft‐switching buck family with six basic soft‐...Figure 9.27 A list of active soft‐switching boost family with six basic soft...Figure 9.28 Illustration of the active soft‐switching buck–boost–buck conver...Figure 9.29 Illustration of the active soft‐switching Zeta‐buck converter de...Figure 9.30 Illustration of the active soft‐switching Ćuk–buck converter der...Figure 9.31 Illustration of the active soft‐switching sepic–buck converter d...

10 Chapter 10Figure 10.1 (a) Buck converter topology and (b) its associated diode and out...Figure 10.2 (a) Boost converter topology, (b) active switch–voltage waveform...Figure 10.3 (a) Buck–boost converter topology, (b) passive switch–voltage wa...Figure 10.4 (a) Ćuk converter, (b) sepic converter, and (c) Zeta converter....Figure 10.5 (a) Voltage‐fed z‐source converter and (b) its equivalent buck c...Figure 10.6 (a) Current‐fed z‐source converter and (b) its equivalent buck c...Figure 10.7 (a) Quasi‐z‐source converter and (b) its equivalent buck convert...Figure 10.8 (a) High step‐down switched‐inductor converter with voltage tran...Figure 10.9 (a) High step‐down switched‐inductor converter with voltage tran...Figure 10.10 (a) Compound step‐down/step‐up switched capacitor converter wit...Figure 10.11 (a) Grafted buck–buck converter and (b) two buck converters in ...Figure 10.12 (a) Grafted boost–boost converter and (b) two boost converters ...

11 Chapter 11Figure 11.1 (a) The second‐order buck–boost converter, (b) Ćuk converter, (c...Figure 11.2 A fourth‐order buck–boost converter with an extra LC filter.Figure 11.3 Conceptual converter topology with a buffer capacitor located be...Figure 11.4 Illustration of the deduction from Zeta converter to Ćuk one.Figure 11.5 Buck and boost converters in topological duality.Figure 11.6 Buck and boost converters in circuital forms, but not in circuit...Figure 11.7 (a) A transmission line model of two wires represented in a two‐...Figure 11.8 Synthesis of the new buck–boost converter with the graft scheme....Figure 11.9 Synthesis of the new boost–buck (Ćuk) converter with the graft s...Figure 11.10 Synthesis of the new buck–boost–buck (Zeta) converter with the ...Figure 11.11 Synthesis of the new boost–buck–boost (sepic) converter with th...Figure 11.12 Synthesis of the new buck‐family converters with the layer sche...Figure 11.13 The buck–boost–buck converter with an external inductor L_x, sho...Figure 11.14 Synthesis of the new boost‐family converters with the layer sch...Figure 11.15 The boost–buck–boost converter with an external capacitor C_x, s...Figure 11.16 Analogy of buck converter to DNA: (a) DNA in double‐helix struc...Figure 11.17 Replication of (a) DNA and (b) buck converter.Figure 11.18 Mutation of buck and boost converters to obtain buck–boost–buck...Figure 11.19 Mutation of buck–boost and boost–buck converters to obtain new ...

12 Chapter 12Figure 12.1 The six typical PWM DC/DC converters.Figure 12.2 General structure of the feedback network with source and load....Figure 12.3 The four basic feedback topologies: (a) series‐shunt, (b) shunt‐...Figure 12.4 Illustration of buck‐boost, Zeta, Ćuk, and sepic converters gene...Figure 12.5 Illustration of the buck‐boost and Zeta converters derived from ...Figure 12.6 Illustration of the Ćuk and sepic converters derived from the bo...Figure 12.7 General converter forms of (a) the buck family and (b) the boost...Figure 12.8 The two‐port network.Figure 12.9 The two types of interconnections of feedback two‐port networks:...Figure 12.10 Two‐port networks with feedback connection for (a) the buck fam...Figure 12.11 (a) h‐Parameter of the buck BCU and (b) g‐parameter of the boos...Figure 12.12 Basic converter units of resonant converters: (a) buck ZCS‐QRC,...

13 Chapter 13Figure 13.1 Conceptual block diagram of converters in cascade connection.Figure 13.2 Schematic diagrams of the buck and boost converters.Figure 13.3 Illustration of the buck‐boost SSC derived from the buck and boo...Figure 13.4 Illustration of the boost‐buck (Ćuk) SSC derived from the boost ...Figure 13.5 Small‐signal models of the SSCs represented in cascaded two‐port...Figure 13.6 (a) y‐Parameter of a PWM DC/DC converter structure and (b) t‐par...Figure 13.7 Illustration of the Zeta converter derived from the buck‐boost, ...Figure 13.8 Illustration of the sepic converter derived from the boost‐buck,...Figure 13.9 Small‐signal models of the SSCs represented in cascaded/cascoded...

14 Chapter 14Figure 14.1 Block diagram of a power converter with PFC.Figure 14.2 The buck ISSC family derived based on the graft scheme. (a) buck...Figure 14.3 The boost ISSC family derived based on the graft scheme. (a) boo...Figure 14.4 The buck‐boost ISSC family derived based on the graft scheme. (a...Figure 14.5 Small‐signal model of the SSC represented in cascaded two‐port n...Figure 14.6 (a) An SSC represented in t‐parameter and with a single‐voltage ...Figure 14.7 The predicted and measured bode plots of the loop gain of the bu...Figure 14.8 The input voltage v_i and current i_i waveforms of the discussed I...Figure 14.9 The control‐to‐output magnitude and phase plots of the rear semi...

15 Chapter 15Figure 15.1 Conceptual block diagrams of two different operating modes in PF...Figure 15.2 The ISSC derived from a buck‐boost semi‐stage and a flyback semi...Figure 15.3 The equivalent circuit of the buck‐boost semi‐stage acts as a PF...Figure 15.4 Conceptual current waveforms of (a) inductor L_pf and (b) active ...Figure 15.5 An equivalent circuit of the isolated flyback converter.Figure 15.6 The magnitude and phase plots of the control‐to‐output transfer ...Figure 15.7 Flyback semi‐stage with a peak current mode control.Figure 15.8 A small‐signal model of the proposed regulator semi‐stage system...Figure 15.9 Output voltage responses of the ISSC to a step duty ratio change...Figure 15.10 The ISSC with an RCD snubber.Figure 15.11 Oscillogram measured from the single‐stage converter (a) the li...Figure 15.12 (a) Measured efficiency versus input voltages, (b) measured pow...Figure 15.13 Control block diagram of the proposed ISSC with an H^∞ con...Figure 15.14 Configuration of a standard H^∞ control problem.Figure 15.15 Illustration of an augmented plant with a robust control.Figure 15.16 The magnitude–frequency plots of F_d(s) under several different ...Figure 15.17 The magnitude–frequency plots of A_u(s) under several different ...Figure 15.18 The magnitude versus frequency plots of sensitivity function S ...Figure 15.19 The magnitude versus frequency plots of the complementary sensi...Figure 15.20 Step responses of the ISSC to the load changes from 0 to 50% an...Figure 15.21 Transient response of the ISSC with a robust controller: (a) th...