Читать книгу Multi-Processor System-on-Chip 1 - Liliana Andrade - Страница 2
Table of Contents
Оглавление1 Cover
4 Foreword
6 PART 1: Processors 1 Processors for the Internet of Things 1.1. Introduction 1.2. Versatile processors for low-power IoT edge devices 1.3. Machine learning inference 1.4. Conclusion 1.5. References 2 A Qualitative Approach to Many-core Architecture 2.1. Introduction 2.2. Motivations and context 2.3. The MPPA3 many-core processor 2.4. The MPPA3 software environments 2.5. Conclusion 2.6. References 3 The Plural Many-core Architecture – High Performance at Low Power 3.1. Introduction 3.2. Related works 3.3. Plural many-core architecture 3.4. Plural programming model 3.5. Plural hardware scheduler/synchronizer 3.6. Plural networks-on-chip 3.7. Hardware and software accelerators for the Plural architecture 3.8. Plural system software 3.9. Plural software development tools 3.10. Matrix multiplication algorithm on the Plural architecture 3.11. Conclusion 3.12. References 4 ASIP-Based Multi-Processor Systems for an Efficient Implementation of CNNs 4.1. Introduction 4.2. Related works 4.3. ASIP architecture 4.4. Single-core scaling 4.5. MPSoC overview 4.6. NoC parameter exploration 4.7. Summary and conclusion 4.8. References
7 PART 2: Memory 5 Tackling the MPSoC Data Locality Challenge 5.1. Motivation 5.2. MPSoC target platform 5.3. Related work 5.4. Coherence-on-demand: region-based cache coherence 5.5. Near-memory acceleration 5.6. The big picture 5.7. Conclusion 5.8. Acknowledgments 5.9. References 6 mMPU: Building a Memristor-based General-purpose In-memory Computation Architecture 6.1. Introduction 6.2. MAGIC NOR gate 6.3. In-memory algorithms for latency reduction 6.4. Synthesis and in-memory mapping methods 6.5. Designing the memory controller 6.6. Conclusion 6.7. References 7 Removing Load/Store Helpers in Dynamic Binary Translation 7.1. Introduction 7.2. Emulating memory accesses 7.3. Design of our solution 7.4. Implementation 7.5. Evaluation 7.6. Related works 7.7. Conclusion 7.8. References 8 Study and Comparison of Hardware Methods for Distributing Memory Bank Accesses in Many-core Architectures 8.1. Introduction 8.2. Basics on banked memory 8.3. Overview of software approaches 8.4. Hardware approaches 8.5. Modeling and experimenting 8.6. Conclusion 8.7. References
8 PART 3: Interconnect and Interfaces 9 Network-on-Chip (NoC): The Technology that Enabled Multi-processor Systems-on-Chip (MPSoCs) 9.1. History: transition from buses and crossbars to NoCs 9.2. NoC configurability 9.3. System-level services 9.4. Hardware cache coherence 9.5. Future NoC technology developments 9.6. Summary and conclusion 9.7. References 10 Minimum Energy Computing via Supply and Threshold Voltage Scaling 10.1. Introduction 10.2. Standard-cell-based memory for minimum energy computing 10.3. Minimum energy point tracking 10.4. Conclusion 10.5. Acknowledgments 10.6. References 11 Maintaining Communication Consistency During Task Migrations in Heterogeneous Reconfigurable Devices 11.1. Introduction 11.2. Background 11.3. Related works 11.4. Proposed communication methodology in hardware context switching 11.5. Implementation of the communication management on reconfigurable computing architectures 11.6. Experimental results 11.7. Conclusion 11.8. References
11 Index
