Читать книгу Multi-Processor System-on-Chip 1 - Liliana Andrade - Страница 3

1 Chapter 1Table 1.1. Input data rates and model complexities for example machine learning ...Table 1.2. Supported kernels in the embARC MLI libraryTable 1.3. Model parameters of the CIFAR-10 CNN graphTable 1.4. Performance data for the CIFAR-10 CNN graph

2 Chapter 2Table 2.1. Cyber-security requirements by application areaTable 2.2. Types of network-on-chip interconnectsTable 2.3. Types of VLIW architectures

3 Chapter 4Table 4.1. Comparison of state-of-the-art CNN acceleratorsTable 4.2. Synthesis results for different configurations of the ASIP

4 Chapter 5Table 5.1. CRM operations’ latency

5 Chapter 7Table 7.1. Setup details

6 Chapter 11Table 11.1. Resource utilization of the communication wrapper in Basic, CS and C...Table 11.2. Resource utilization of the communication wrapper in Basic, CS and C...Table 11.3. Size of hardware task context for each benchmark applicationTable 11.4. Comparison of total execution time (FPGA cycles) and its variation o...Table 11.5. Comparison of average extraction and restoration times (FPGA cycles)...Table 11.6. Comparison of average context switch latency (FPGA cycles) between C...Table 11.7. Task migration time between A5SOC and ZC706