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The fabrication technology of a semiconductor p-n junction diode involving different steps is displayed diagrammatically in Figure 1.14 [10,31]. This planar fabrication technology consists of thermal oxidation of Si wafer to grow SiO₂ as the first step (a), second step (b) is the application of photoresist (PR) over SiO₂, third step (c) is the patterning of PR with the help of optical lithography, fourth step (d) is the etching out of SiO₂ and exposing selective surface of Si wafer, fifth step (e) is removal of the PR, sixth step (f) involves doping of impurity atoms selectively to produce p-n semiconductor junction, and the last step (g) is the metallization of the top layer and of the back side for electrical interconnects [10,31]. For the growth of high quality SiO₂, wet or dry thermal oxidation process can be used.

Figure 1.14 Schematic shows diagrammatically the various steps involved in fabrication of p-n junction diode. The first step (a) is the thermal oxidation for the growth of SiO₂ layer, second step (b) is the application of resist over the grown SiO₂ layer, third step (c) is the patterning of resist, fourth step (d) involves etching out SiO₂, fifth step (e) is the removal of the photoresist. After this, step (f) involves doping of foreign atoms by diffusion or ion-implantation and step (g) is the metallization step on the top layer and bottom side of the Si wafer for electrical contacts.

Dry oxidation is performed using dry oxygen for growing thinner oxide layers and produces high-grade features at Si-SiO₂ interface. Wet thermal oxidation takes place in presence of water vapour and is applied to grow thicker oxide layers because of its high growth rate in comparison to dry thermal oxidation. Growth of high-quality pin-hole free SiO₂ layer on Si wafer is an essential requirement in the production and monolithic integration of integrated circuitry (IC) [10,31]. High-quality SiO₂ layer works as device isolation material which prevents short-circuiting amongst various devices fabricated on a single Si wafer. It can also be used as a mask to define area covered under the junction in the fabrication of a semiconductor p-n junction [32-35]. As shown in Figure 1.14(b), an organic photoactive material called photoresist (PR) is applied uniformly over thermally grown dielectric oxide by a spin-coated at the suitable rounds per minute (rpm) of spinning [36,37]. PR adhesion on the wafer is improved through hardening the resist by evaporation of the solvent by baking the PR-spun wafer at 80°C - 90°C [31]. Next, the patterned mask is used to expose the wafer by illumination of UV-light [31]. A patterned mask is an optical mask or photomask used in optical lithography consisting of pattern of the integrated circuitry or IC. It is usually a glass substrate coated with the chrome (Cr) and a resist layer [38-40]. The opaque parts in an optical mask consist of Cr-metal coating responsible for the shadows casted during exposure of Si wafers. The exposed region of PR-spun wafer or the chemistry of the PR-spun part that is exposed to the radiation of UV-light changes according to the PR used as shown in Figure 1.14(c). A photoresist can be positive or negative depending on whether it softens or hardens on exposure to light [36,37,41]. The PR gets polymerized on exposure to light and it becomes difficult to remove it in an etchant. In the next step, the development process is followed by immersing the wafer in the developer solution [31,42]. Here, unexposed region or part of the PR-spun wafer that is not exposed to light because of falling under the opaque part of the optical mask dissolves in the developer solution and is washed away. On the other hand, the exposed region remains intact in the developer solution and is again baked under optimized time duration in the temperature range of 120°C-180°C. This not only improves the adhesion of the exposed part but also makes it robust for the next step of etching process to remove the oxide selectively. The unmasked oxide layer is removed by an etchant buffered hydrofluoric (BHF) acid as shown in step (d) of Figure 1.14. Finally, the PR is ashed-off by the physical process of plasma-asher utilizing oxygen (O₂) plasma [43,44] or through a chemical solution as shown in step (e) of Figure 1.14. As the last step of fabrication of p-n junction, diffusion or ion-implantation is performed as per the requirements as shown in step (f) of Figure 1.14, and followed by metallization for top and back contacts fabrication (step (g) of Figure 1.14). In step (f), solid-state diffusion process [10,18,31] dopes the opposite type of impurity or foreign atoms in high concentration into the oxide-layer free part of the relevantly doped substrate. For example, p-type of foreign atoms are doped in an n-type of substrate and vice-versa to form p-n junction. As a matter of fact, due to lateral straggle or distribution of implanted ions or lateral diffusion mechanisms [10,18,31], the width of the doped part is slightly larger than the unprotected area. Ion-implantation can be performed with a wide selection of masking materials inclusive of oxide, polysilicon, PRs and metals, low temperature process, such that, even organic materials like PRs can be used for masking, excellent lateral uniformity in addition to offering precise control of depth profile and doses [10,31,45]. After introduction of oppositely natured impurities in the substrate, top and back-contacts are deposited by sputtering, e-beam evaporation, thermal evaporation or even chemical vapour deposition forming the process of metallization [46-50]. This forms ohmic contacts and interconnects by depositing noble metals that include gold (Au), silver (Au) or even low cost metals, such as, copper (Cu) and nickel (Ni). Blanket deposition is required for metallization on the back-side of the wafer. Deposition is usually followed by low-temperature annealing for promoting adhesion and low-resistance interface between semiconductor and the metallic layer.

Crystalline silicon solar cell (c-Si)–based technology [51-57] has been recognized as the only environment-friendly viable solution to replace traditional energy sources for power generation. It is a cost-effective, renewable and long-term sustainable energy source. There have been constant efforts in reducing the manufacturing cost of solar panel technology, which is about three to four times higher in comparison to traditional carbon-based fuels [58-60]. In the manufacturing domain, fabrication of three basic c-Si solar cell configurations can be utilized, which are differentiated in the manner of generation of electron-hole (E-H) pairs on exposure to sunlight. The three basic c-Si solar cell configurations are monofacial [57,62-64] bifacial [65-69] and back-contacted [70,71] solar cell configurations as shown in Figure 1.15(a), 1.15(b) & 1.15(c).

In the monofacial solar cell configuration as shown in Figure 1.15(a), the top point contacts above the surface of antireflection (AR) film form metallic electrical contacts. On the other hand, the rear surface consists of completely covering thin metallized layer, which serves as the second electrode. This is the dominant configuration used in commercial manufacturing of c-Si solar panel technology. The bifacial solar cell consists of n-doped emitter on both top and rear sides of the p-type substrate such that both front and back surface metallic grids are similar as shown in Figure 1.15(b). Both top and bottom sides are capable of generating E-H pairs. The requirement of high efficiency of these solar cells is to have high lifetime of the minority carriers. In the third type shown in Figure 1.15(c), the back-contacted solar cell configuration, n/p floating junctions are formed on both sides such that p⁺-doped and n⁺-doped regions exist in each of the layers. In this geometry, the top surface does not consist of any metallic grid. The minority carrier lifetime in these types of solar cells should be high so that the E-H pairs can diffuse to the back-side of the cell and collectively form external current. The back-contacted solar cell is the most efficient configuration of commercial solar cell and its manufacturing requires multiple complicated steps. Figure 1.16 shows the various steps involved in the fabrication of a monofacial solar cell. Similarly, bifacial and back-contacted solar cells can be fabricated utilizing various growth, patterning and deposition steps as discussed in general fabrication methodology in Figure 1.14 schematically.

Figure 1.15 (a) Shows the schematic of (a) monofacial solar cell, (b) bifacial solar cell and (c) back-contacted solar cell configurations.

Figure 1.16 Fabrication steps involved in the preparation of a monofacial solar cell.

The generation of electricity by impinging light on a semiconductor material requires production of electrons and holes such that electrons in the valence band become free and jump to the conduction band by absorbing energy [72-74]. Thus, jumping of highly energetic electrons to different material generates an electromotive force (EMF) converting light energy into electrical signals. This is known as the photovoltaic (PV) effect. The first PV cell was fabricated by Charles Fritts in 1883 by depositing a thin layer of gold (Au) over the semiconductor material selenium (Se) to form junctions [72-74]. This first fabricated solar cell was only 1% efficient. A solar cell or PV cell is basically a p-n junction exhibiting nonlinear current-voltage (I-V) characteristics. Bell Laboratories, USA, developed the first practical solar cell in 1954 by fabrication of a diffused Si p-n junction with 6% efficiency. Si is widely used in PV cell technology since it is cheaper, abundant and Si-fabrication technology is highly developed [72-74]. First of all, polished Si wafers cut from highly pure industrial grade Si boules are prepared which can be single-crystalline, polycrystalline or even amorphous. After wafer procurement/fabrication, Si is doped selectively to make p-n junctions and is processed to furnish a solar cell. The various methods of fabrication of solar cells are listed as follows [72-74],

1 (i) Screen printed fabrication technology

2 (ii) Buried contact fabrication technology

A process flow chart for fabrication of solar cell panels has been shown in Figure 1.17. The PV technology is based on the photoelectric effect in which a doped semiconductor produces electricity as a result of electron-hole generation on illumination of solar radiation [4,5,9,72-74]. The main merits of PV technology include reduced dependency on orthodox sources of energy of fossil fuels, pollution-free energy technology with zero emission, significantly reduced operational and maintenance costs, long life of solar panels of over twenty years with robust & reliability features. Moreover, system modularity provides the flexibility of enhancement of power production by simply increasing the number of solar panels. A solar energy production plant consists of generators or the solar panels and a frame or hard-casing for mounting the panels in a particular orientation or angle. This is supported by an electrical power control system and an energy storage system frequently nested in industries, houses, factories, big farmhouses, universities, colleges, offices and buildings. The basic component of a PV generator is the solar cell which converts solar radiation into electrical power.

Figure 1.17 Shows the process flow for fabrication of solar cells to manufacture photovoltaic (PV) array. Various steps involved in the fabrication process have been demonstrated pictorially.

On illumination of light on the solar cell, E-H pairs arise in both the p- and n-type regions [4,5,9,72-74]. As discussed previously, an internal electric field is developed due to the charge carriers in the semiconductor junction. It pushes the extra electrons to segregate from electronic charge pairing due to the absorption of optical energy and makes them move in a direction opposite to the movement of holes. This electric field is directed from p-type region to n-type region, and as a result, electric force prevents them from transportation in the reverse direction after crossing the electric barrier. For electrical transport, the junction is interconnected by an external conductor making a closed circuit as shown in Figure 1.18. In this circuit on illumination with light, current flows from n-type block or layer with higher potential to another n-type block or layer at a lower potential. The saga of electrical conduction lies in the fact that an electron in the valence band absorbs sufficiently energetic photon to get excited to the conduction band, a case typical for semiconductor materials with bandgap energies slightly higher than the metals [4,5,9,72-74].

Figure 1.18 Schematic shows the electrical contacting of n-type layers with current flowing from high potential to low layer on illumination of light. The inset shows the electron jump from valence band (VB) to conduction band (CB) on absorption of optical energy in form of the quanta of light.

An important fact is that the larger the surface area of the solar panel, the larger is the current produced. The genesis is that the region surrounding the p-n junction works as a factory of charges, while holes and electrons generating in far-flung areas, means away from the junction, recombine because there is no force supplied by an electric field to drive them off. This is the main reason for non-conversion of most of the solar energy into electrical energy. Therefore, the solar energy is responsible for segregation of charge carriers, recombination of hole-electron charge carriers leading to annihilation, transmission of solar energy, reflection from the front contacts on surface of the panel in addition to the shadow effects.

Thousands and millions of solar cells fabricated on a solar module are assembled on a single surface called as the panel. Many panels are assembled or connected in series to form an array. Several of such arrays are connected in parallel to form the PV generator for obtaining desired output of electrical power. As a matter of fact, due to subtle manufacturing defects, the solar cells in the modules are not identical and hence no two blocks connected in parallel can have the same magnitude of voltage. This results in generation of a current flowing from cells at higher potential to cell blocks having lower voltages. This creates mismatch losses due to the fact that a portion of converted power is lost inside the module itself. Similar problems arise in case of arrays connected in parallel because of dissimilarity of modules, shadow effects, defects and possessing different irradiance issues. To avoid these problems, by-pass diodes can be additional electrical components in the non-linear circuitry to short-circuit the shadowed or maligned part of the module. Mismatch losses due to dissimilar electrical features of the cells can also be measured by solar irradiances on shadowed or damaged solar cells. These cells block the current produced by other solar cells, are subject to the voltage of other cells and cause local overheating and damages.

Nowadays, crystalline Si solar cells are used with efficiency of 14%-17%, which can be single crystalline and polycrystalline silicon solar cells [4,5,9,72-74]. These are derived by chopping-off slices of wafers from the cylindrical ingot. Microgrooves are patterned over and above the top surface for minimizing losses due to reflection. In polycrystalline silicon panels, differently oriented silicon crystals based solar cells respond typically on illumination in case of irradiances and are preferably square-shaped.

Another species of solar cell is based on semiconductor thin films (few μm) deposited on polymer or glass flexible substrates [75-78]. The thin film materials are inclusive of amorphous Si [76,79], semiconductor material gallium arsenide (GaAs) [80,81], cadmium-telluride (CdTe) [82] and copper-indium-gallium-selenide (CIGS) [83,84] alloy materials. Amorphous Si (a-Si) offers reduced costs than crystalline Si solar cell technology. It is applied where light-weight solar panels are required and in case of curved surfaces. It possesses low efficiency and the cell performance also deteriorates with time. An extended application of a-Si is the tandem solar cell in which amorphous film is coupled with one or more multi-junction crystalline layers. The variety of tandem solar cells are based on organic solar cell, inorganic solar cell and hybrid solar cells. Organic solar cells are under intense research due to significantly low costs involved but, however, suffer from the problem of degradation within a short span of one or two weeks generally. CdTeS solar cell consists of the p-type layer (CdTe) and n-type CdS layer forming a heterojunction solar cell possessing an efficiency of ~11% in case of industrial grade cells [85,86]. GaAs is next grade semiconductor material finding many applications in high-speed electronics, space applications and optoelectronics industry. Alloy-based solar materials include copper-indium-selenide (CIS), copper-indium-gallium-selenide (CIGS) and copper-indium-gallium-selenide-sulphur (CIGSS) [87]. The two types of PV plants are stand-alone plants and grid-based plants. Standalone plants are not connected to the grid and the core structure consists of PV panels and an energy storage system which ensures electric power supply when sunlight is not available or poorly available. A PV generator produces direct electric current (DC) power supply [88-90]. In case, an alternate current (AC) power supply is required to meet the requirements at the demand end, an inverter for conversion of DC to AC power supply is required [88-90]. The grid-connected plants fetch electric power from the grid in the case of PV generators not being efficient enough to produce enough power for meeting the clients’ requirements. On production of surplus electric power, the excess can be stored in the grids and can be used for further utilization. This is not a centralized power technology rather it is a distributed energy production technology. This offers the advantages of reduced transmission losses in addition to decreased expenses on electrical transport systems.