Читать книгу Electronic Packaging Science and Technology - King-Ning Tu - Страница 13

As the trend of miniaturization in Si technology slows down, microelectronics industry has been looking for ways to keep the downsizing momentum going, meaning to go to more‐than‐Moore! [1–3] The critical feature size in Si devices has already reached nanoscale, below 10 nm. Hence, it is harder and harder to make transistor circuits on a Si chip smaller and smaller without a large cost increase. At present, the most promising way to extend Moore’s law is to go from 2D IC to 3D IC. Actually, the paradigm change has occurred more than 10 years ago, but 3D IC is not in mass production, because of cost and reliability.

In semiconductor manufacturing, because the product quantity is extremely large, so high yield and high reliability are critically important. Low yield will increase cost, and poor reliability will lead to recall; one example is the battery failure of cell phones. For any consumer electronic product in mass production, the concern of reliability is critical, especially the electronic packaging in 3D IC for advanced consumer electronic products, which are widely used now for distance teaching and home office.

In this introductory chapter, we explain what is electronic packaging? Also, what are the science and engineering in it, especially those relate to reliability? If we want to add more functions to hand‐held devices, the operations of memory, logic, and special functions must be increased. At the same time, power as well as battery capacity must be increased too. A larger size battery will squeeze the volume of the rest of the device, which makes the heating problem worse. To remove heat, we must have a temperature gradient. If we consider a temperature difference of 1 °C across a microstructure of 10 μm in diameter, the temperature gradient is 1000 °C/cm, which will induce thermomigration. In turn, Joule heating will enhance electromigration, and thermo‐stress will induce stress‐migration. While these are time‐dependent events, they are of major reliability concern.

Figure 1.4 is a scanning electron microscopy (SEM) image of the cross‐section of a 2.5D IC test device. It has only two pieces of Si chips stacking on a polymer board. Electrically, they are interconnected by three sets of solder joints. At the bottom or on the outside of the polymer board is the set of the largest solder balls of diameter up to 760 μm, which is called the ball‐grid‐array (BGA). These balls allow the test device to be connected to the circuits on a printed circuit board. Within the polymer board, there are Cu wirings, as well as Cu plated‐through‐holes, which are not shown in the image. On top of the polymer board, there is the second set of flip chip solder balls of diameter about 100 μm, the so‐called C‐4 (controlled collapse chip connection) solder balls, connecting the board to the first Si chip, which is the “interposer.” In this test device, there is no transistor on the interposer, which is passive and serves only as a substrate without introducing thermal stress to the active Si chip on the top. Often this test device is called 2.5D IC due to the fact that the interposer has no transistors. If the interposer has transistors, it becomes 3D IC.

Figure 1.4 Scanning electron microscopy (SEM) image of the cross‐section of a 3D IC test device. It has only two pieces of Si chips stacking on a polymer board.

In the interposer, there are arrays of vertical through‐Si‐vias (TSV) plated with Cu, making connections to the third arrays of solder joints of diameter about 10–20 μm, the so‐called micro‐bumps or μ‐bumps, which join the interposer to the top Si chip. The top Si chip is an active device chip, so it has transistors. The thickness of the device in Figure 1.4 is about that of a US penny. The thinness of the device is a critical requirement due to the limit of form factor of mobile consumer electronic products. Consequently, the thickness of Si chips is thin too. The thickness of the Si interposer is about 50 μm, which is much thinner than that of a convention Si chip of 200 μm in thickness. The thin interposer has caused the warpage problem, as well as the heat conduction issue, to be discussed in the later chapters. The diameter of the TSV in the interposer is about 5 μm, so the aspect ratio of the TSV is 10.

In the above example, besides the active Si chip, the rest, which includes the interposer, can be regarded as electronic packaging. The packaging enables the Si chip to function, as well as to allow us, to interact with the outside world. In the packaging, it is worth mentioning that between two sets of solder joints of different sizes, there should be a redistribution layer (RDL) structure for circuit fan‐out. It increases the number of input–output (I/O) contacts of a circuit in going from a low density of solder joints to a high density of solder joints. The higher the density of I/O, the better the resolution of frequency of a digital electromagnetic wave, because each I/O is designed to transmit a small width of the wave.

At the moment, there are two critically important challenges in electronic packaging technology. The first is the need of denser and denser I/O, which means the diameter of micro‐bump and the pitch between them has to be reduced. As to be shown in Chapter 3, hybrid‐bonds consist of Cu‐to‐Cu bonds together with dielectric‐to‐dielectric bonds are being developed. The second is Joule heating and heat dissipation, which will be discussed in Chapter 9.

About the increase of I/O, from BGA to C‐4 joints, there is a RDL of Cu wires in the upper part of the polymer board. From C‐4 joints to μ‐bumps, there is an RDL of Cu wires at the lower part of the interposer chip. This second RDL is invisible in the figure, but it is new in 3D IC because it does not exist in 2D IC devices, where typically there are only two levels of solder joints. The failure of the new RDL is of concern.

Figure 1.5a and b show synchrotron radiation tomographic images of a 3D IC and part of a 2.5D IC device, respectively. The latter has a length about 4 mm, and a thickness and a height of about 0.5 mm. Due to the weak absorption of X‐ray, the two Si chips and the polymer substrate become invisible. We can see the vertical TSV pillars. Also, the solder balls and the Cu wires are shown clearly. In Figure 1.5a, by using a pair of the BGA balls as the cathode and the anode and by passing 50 mA at 100 °C, following the arrows which indicate the conduction path, we can study time‐dependent failures caused by electromigration and Joule heating, to be discussed in Chapter 10.

Figure 1.5 (a) Synchrotron radiation tomographic images of a similar device as shown in Figure 1.1. Due to the weak absorption of X‐ray, the two Si chips and the polymer substrate become invisible. But the solder balls and the Cu wires are shown clearly. (b) Synchrotron radiation tomographic image of a 2.5D IC device, having a length about 4 mm, and a thickness and a height of about 0.5 mm. The vertical TSV pillars can be seen.

Why do we emphasize electromigration and Joule heating? This is because electronic devices are current–voltage (I‐V) devices, so the applied electric current goes in and out of the devices in an open system. It causes Joule heating and electromigration, which are of key reliability concern. Figure 1.6 is a schematic diagram of the cross‐section of a typical 3D IC device. The structure, in essence, is the same as that shown in Figure 1.4, except that on the right‐hand side, there is a stack of memory chips on a logic chip as the CPU. If we replace the stack by an optical or compound semiconductor or MEMS chip, it becomes heterogeneous integration.

Figure 1.6 Schematic diagram of the cross‐section of a typical 3D IC device.

In comparing the structure of 3D IC to that of 2D IC, the difference is the stacking of multilayer of chips and the interconnects using TSV and μ‐bumps. On processing TSV, the thinner the chip, the easier the drilling of vias. On making μ‐bumps, its melting point should be lower than that of C‐4 joints, so that the latter will not melt upon the melting of the former. Thus, the basic challenges are that the wafer is thinner and the processing temperature is lower.

From the viewpoint of packaging technology, we may say that the essence or the major challenge in 3D IC is to scale down the dimension of packaging structures so that it can match those in the chip technology. There is no Moore’s law in packaging technology, so it has room to shrink.

What are the key functions of electronic packaging? The cell phone held in our hands is a movable electronic packaging product or a mobile computer, which enables us to compute and to communicate with the world around us. The set of chips in the cell phone can be arranged horizontally, side by side, but it takes space. Or they can be arranged vertically, one on top of the other, this is called 3D IC, and it reduces the form factor and takes less space. However, heat dissipation in 3D IC is harder because the packing is denser. When over‐heat occurs, it induces reliability problems. Over all, the product should be electrically, mechanically, chemically, and thermally stable.