Читать книгу Reversible and DNA Computing - Hafiz M. H. Babu - Страница 13

ALUarithmetic logic unitBCDbinary coded decimalBJSBabu‐Jamal‐SaleheenCADcomputer‐aided designCSAcarry skip adderCLAcarry look‐ahead adderCPUcentral processing unitDAGdirected acyclic graphDFSdepth first searchDSPdigital signal processingDNAdeoxyribonucleic acidDRAGDNA‐based reversible AND gateDRNGDNA‐based reversible NOT gateDROGDNA‐based reversible OR gateDXRGDNA‐based reversible Ex‐OR gateDRFADNA‐based reversible full adderDSMdeep sub micronESOPexclusive sum‐of‐productsFPGAfield programmable gate arrayF2GFeynman double gateFGFeynman gateFRGFredkin gateFPUfloating‐point unitFPGAfield programmable gate arrayFTFAfault‐tolerant full adderHLNHasan‐Lafifa‐NazirHPPHamiltonian path problemIRinstruction registerMIGmodified Islam gateMOAmulti‐operand additionNFTnew fault tolerantPCRpolymerase chain reactionPFApartial full adderPGPeres gatePALprogrammable array logicPLAprogrammable logic arrayPIPOparallel‐in parallel‐outPISOparallel‐in serial‐outPPGpartial product generationPROMprogrammable read‐only memoryQCAquantum‐dot cellular automataLDPClow‐density parity‐checkRAMrandom access memoryRFDreversible fault‐tolerant decoderRFTPLAreversible fault‐tolerant programmable logic arrayRGreversible gateSOPsum‐of‐productsSISOserial‐in serial‐outSIPOserial‐in parallel‐outSNFAsingle NFT full adderTBtestable blockTGToffoli gateUPPGuniversal parity‐preserving gate