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The number of output bits is relatively small compared to the number of input bits in most computing tasks. For example, in a decision problem, the output is only one bit (yes or no) and the input can be as large as desired. However, computational tasks in communication, computer graphics, digital signal processing, and cryptography require that all the information encoded in the input should be preserved in the output. One might expect to get further speed‐ups by adding instructions to allow computation of an arbitrary reversible function. The problem of chaining such instructions together provides one motivation for studying reversible computation and reversible logic circuits, that is, logic circuits comprising of gates computing reversible functions.

Reversible logic is an emerging research area. Interest in reversible logic is sparked by its applications in several technologies, such as quantum, CMOS, optical and nanotechnology. Reversible implementations are also found in thermodynamics and adiabatic CMOS. Power dissipation in modern technologies is an important issue, and overheating is a serious concern for both manufacturer (impossibility of introducing new, smaller scale technologies, limited temperature range for operating the product) and customer (power supply, which is especially important for mobile systems). One of the main benefits that reversible logic is theoretically zero power dissipation in the sense that, independently of underlying technology, irreversibility means heat generation.

Reversible circuits are also interesting because the loss of information associated with irreversibility implies energy loss. Some reversible circuits can be made asymptotically energy‐lossless as their delay is allowed to grow arbitrarily large. Currently, energy losses due to irreversibility are dwarfed by the overall power dissipation, but this may change if power dissipation improves. In particular, reversibility is important for nanotechnologies where switching devices with gain are difficult to build.

The advancement in higher‐level integration and fabrication process has emerged in better logic circuits and energy loss has also been dramatically reduced over the last decades. This trend of reduction of heat in computation also has its physical limit. It is well understandable that in logic computation every bit of information loss generates joules of heat energy where is Boltzmann's constant of and is the absolute temperature of the environment. At room temperature, the dissipating heat is around . Energy loss limit is also important as it is likely that the growth of heat generation causing information loss will be noticeable in future.

Reversible circuits are fundamentally different from traditional irreversible ones. In reversible logic, no information is lost, i.e., the circuit that does not lose information is reversible. Zero energy dissipation would be possible if the network consists of reversible gates only. Thus, reversibility will be an essential property for the future circuit design. Quantum computation is also gaining popularity as some exponentially hard problems can be solved in polynomial time. It is known that quantum computation is reversible. Thus, research in reversible logic is helpful for the development of future technologies; it has the potential to methods of quantum circuit construction resulting in more powerful computers. Quantum technology is not the only one where reversibility is used.

Reversible logic has also found its applications in several other disciplines such as nanotechnology, DNA technology, and optical computing. In computers, numbers are stored in straight binary format. Due to inherent characteristics of floating‐point numbers and limitations on storing formats, not all floating‐point numbers can be represented with desired precision. So, the computing in decimal format is gaining popularity because precision can be avoided in this format.

This part starts with some backgrounds and preliminary studies about reversible logic synthesis and some popular reversible gates that are given in Chapter 1. Many of the reversible gates are included in different chapters. Some approaches of designing different reversible adders (full adder, carry skip adder, carry look‐ahead adder, and ripple carry adder) and subtractor circuits are given in Chapter 2. Chapter 3 presents the design of a reversible signed multiplier which is based on Booth's recoding. A design of sequential division circuit using reversible logic is shown in Chapter 4. The hardware has its application in the design of a reversible arithmetic logic unit. The design of a reversible low power n‐bit binary comparator is discussed in Chapter 5. Chapter 6 shows the designs of reversible latches and flip‐flops are presented, which are being optimized in terms of quantum cost, delay, and garbage outputs. The contents of this chapter have optimized the reversible sequential circuit designs in terms of reversible gates and garbage outputs. The designs of reversible D latch and D flip‐flop are also discussed with asynchronous set/reset capability. A reversible design for both ‐bit synchronous and asynchronous counter is described in Chapter 7. This chapter also describes a synthesized design of the reversible counter that is optimized in terms of quantum cost, delay, and garbage outputs.

Chapter 8 is divided into two parts, namely, reversible barrel shifter and reversible shift register. In the first part of this chapter, the design methodology of a reversible barrel shifter is presented. In the second part of this chapter, reversible logic synthesis is carried out for SISO shift register.The key contribution of this part is the reversible realization of SIPO, PISO, PIPO and universal shift registers. Two reversible gates have been introduced in Chapter 9, named as R‐I gate and R‐II gate, for realizing reversible combinational logic circuits. These two gates can be used for realization of basic logical functions such as AND, XOR, and MUX. Chapter 10 is also divided into two parts, namely, reversible field programmable gate array (FPGA) and reversible programmable logic array (PLA). In the first part of this chapter,a design of reversible architecture of the logic element of Plessey FPGA is described, which results in significant power savings. In the second part of this chapter, a design of reversible PLA is described, which is able to realize multi‐output ESOP (exclusive‐OR sum‐of‐product) functions by using a reversible gate, called MG (MUX gate).

Chapter 11 is also divided into two parts namely reversible random access memory (RAM) and reversible programmable read‐only memory (PROM). In the first part of this chapter, the reversible logic synthesis of RAM is described with a reversible gate named as FS. In the way of designing a reversible RAM, an reversible decoder, reversible D flip‐flop, and write‐enabled master–slave D flip‐flops are also designed. In the second part of this chapter, a reversible PROM design is described. A reversible decoder named ITS and another reversible gate TI are also introduced. In addition, for designing the reversible PROM, an AND‐plane and an Ex‐OR plane are also described. The design of programmable reversible logic gate structures is presented in Chapter 12, which implements ALU and presents its different uses. Finally, a reversible control unit is presented in Chapter 13. Two reversible gates, namely HL gate and BJ gate, are introduced to design reversible decoder and JK flip‐flop.