Читать книгу Reversible and DNA Computing - Hafiz M. H. Babu - Страница 2
Table of Contents
Оглавление1 Cover
3 Preface
5 Acronyms
7 Part I: Reversible Circuits 1 Reversible Logic Synthesis 1.1 Reversible Logic 1.2 Reversible Function 1.3 Reversible Logic Gate 1.4 Garbage Outputs 1.5 Constant Inputs 1.6 Quantum Cost 1.7 Delay 1.8 Power 1.9 Area 1.10 Hardware Complexity 1.11 Quantum Gate Calculation Complexity 1.12 Fan‐Out 1.13 Self‐Reversible 1.14 Reversible Computation 1.15 Area 1.16 Design Constraints for Reversible Logic Circuits 1.17 Quantum Analysis of Different Reversible Logic Gates 1.18 Summary 2 Reversible Adder and Subtractor Circuits 2.1 Reversible Multi‐Operand n‐Digit Decimal Adder 2.2 Reversible BCD Adders 2.3 Reversible BCD Subtractor 2.4 Summary 3 Reversible Multiplier Circuit 3.1 Multiplication Using Booth's Recoding 3.2 Reversible Gates as Half Adders and Full Adders 3.3 Some Signed Reversible Multipliers 3.4 Design of Reversible Multiplier Circuit 3.5 Summary 4 Reversible Division Circuit 4.1 The Division Approaches 4.2 Components of Division Circuit 4.3 The Design of Reversible Division Circuit 4.4 Summary 5 Reversible Binary Comparator 5.1 Design of Reversible ‐Bit Comparator 5.2 Summary 6 Reversible Sequential Circuits 6.1 An Example of Design Methodology 6.2 The Design of Reversible Latches 6.3 The Design of Reversible Master–Slave Flip‐Flops 6.4 The Design of Reversible Latch and the Master–Slave Flip‐Flop with Asynchronous SET and RESET Capabilities 6.5 Summary 7 Reversible Counter, Decoder, and Encoder Circuits 7.1 Synthesis of Reversible Counter 7.2 Reversible Decoder 7.3 Summary 8 Reversible Barrel Shifter and Shift Register 8.1 Design Procedure of Reversible Bidirectional Barrel Shifter 8.2 Design Procedure of Reversible Shift Register 8.3 Summary 9 Reversible Multiplexer and Demultiplexer with Other Logical Operations 9.1 Reversible Logic Gates 9.2 Designs of Reversible Multiplexer and Demultiplexer with Other Logical Operations 9.3 Summary 10 Reversible Programmable Logic Devices 10.1 Reversible FPGA 10.2 Reversible PLA 10.3 Summary 11 Reversible RAM and Programmable ROM 11.1 Reversible RAM 11.2 Reversible PROM 11.3 Summary 12 Reversible Arithmetic Logic Unit 12.1 Design of ALU 12.2 Design of Reversible ALU 12.3 Summary 13 Reversible Control Unit 13.1 An Example of Control Unit 13.2 Different Components of a Control Unit 13.3 Summary
8 Part II: Reversible Fault Tolerance 14 Reversible Fault‐Tolerant Adder Circuits 14.1 Properties of Fault Tolerance 14.2 Reversible Parity‐Preserving Adders 14.3 Summary 15 Reversible Fault‐Tolerant Multiplier Circuit 15.1 Reversible Fault‐Tolerant Multipliers 15.2 Summary 16 Reversible Fault‐Tolerant Division Circuit 16.1 Preliminaries of Division Circuits 16.2 The Division Method 16.3 Components of a Division Circuit 16.4 The Design of the Division Circuit 16.5 Summary 17 Reversible Fault‐Tolerant Decoder Circuit 17.1 Transistor Realization of Some Popular Reversible Gates 17.2 Reversible Fault‐Tolerant Decoder 17.3 Summary 18 Reversible Fault‐Tolerant Barrel Shifter 18.1 Properties of Barrel Shifters 18.2 Reversible Fault‐Tolerant Unidirectional Logarithmic Rotators 18.3 Fault‐Tolerant Unidirectional Logarithmic Logical Shifters 18.4 Summary 19 Reversible Fault‐Tolerant Programmable Logic Devices 19.1 Reversible Fault‐Tolerant Programmable Logic Array 19.2 Reversible Fault‐Tolerant Programmable Array Logic 19.3 Reversible Fault‐Tolerant LUT‐Based FPGA 19.4 Summary 20 Reversible Fault‐Tolerant Arithmetic Logic Unit 20.1 Design of ‐bit ALU 20.2 Summary 21 Online Testable Reversible Circuit Using NAND Blocks 21.1 Testable Reversible Gates 21.2 Two‐Pair Rail Checker 21.3 Synthesis of Reversible Logic Circuits 21.4 Summary 22 Reversible Online Testable Circuits 22.1 Online Testability 22.2 The Design Approach 22.3 Summary 23 Applications of Reversible Computing Why We Need to Use Reversible Circuits Applications of Reversible Computing 23.1 Adiabatic Systems 23.2 Quantum Computing 23.3 Energy‐Efficient Computing 23.4 Switchable Program and Feedback Circuits 23.5 Low‐Power CMOS 23.6 Digital Signal Processing (DSP) and Nano‐Computing
9 Part II: DNA Computing 24 Background Studies About Deoxyribonucleic Acid 24.1 Structure and Function of DNA 24.2 DNA Computing 24.3 Relationship of Binary Logic with DNA 24.4 Welfare of DNA Computing 24.5 Summary 25 A DNA‐Based Approach to Microprocessor Design 25.1 Basics of Microprocessor Design 25.2 Characteristics and History of Microprocessors 25.3 Methodology of Microprocessor Design 25.4 Construction of Characteristic Tree 25.5 Traversal of the Tree 25.6 Encoding of the Traversed Path to the DNA Sequence 25.7 Combination of DNA Sequences 25.8 Decoding the Output String 25.9 Processor Evaluation 25.10 Post‐Processing 25.11 Gene Pool Update 25.12 Summary 26 DNA‐Based Reversible Circuits 26.1 DNA‐Based Reversible Gates 26.2 DNA‐Based Reversible NOT Gate 26.3 DNA‐Based Reversible Ex‐OR Gate 26.4 DNA‐Based Reversible AND Gate 26.5 DNA‐Based Reversible OR Gate 26.6 DNA‐Based Reversible Toffoli Gate 26.7 Realization of Reversible DNA‐Based Composite Logic 26.8 Summary 27 Addition, Subtraction, and Comparator Using DNA 27.1 DNA‐Based Adder 27.2 DNA‐Based Addition/Subtraction Operations 27.3 DNA‐Based Comparator 27.4 Summary 28 Reversible Shift and Multiplication Using DNA 28.1 DNA‐Based Reversible Shifter Circuit 28.2 DNA‐Based Reversible Multiplication Operation 28.3 Summary 29 Reversible Multiplexer and ALU Using DNA 29.1 DNA‐Based Reversible Multiplexer 29.2 DNA‐Based Reversible Arithmetic Logic Unit 29.3 Summary 30 Reversible Flip‐Flop Using DNA 30.1 The Design of a DNA Fredkin Gate 30.2 Simulating the Fredkin Gate by Sticking System 30.3 Simulation of the Reversible D Latch Using DNA Fredkin Gate 30.4 DNA‐Based Biochemistry Technology 30.5 Summary 31 Applications of DNA Computing 31.1 Solving the Optimization and Scheduling Problems Like the Traveling Salesman Problem 31.2 Parallel Computing 31.3 Genetic Algorithm 31.4 Neural System 31.5 Fuzzy Logic Computation and Others 31.6 Lift Management System 31.7 DNA Chips 31.8 Swarm Intelligence 31.9 DNA and Cryptography Systems 31.10 Monstrous Memory Capacity 31.11 Low‐Power Dissipation 31.12 Summary
10 Conclusion
11 Copyright Permission of Third‐Party Materials
12 Bibliography
13 Index
