Читать книгу Reversible and DNA Computing - Hafiz M. H. Babu - Страница 4

1 Chapter 1Figure 1.1 A reversible gate.Figure 1.2 Popular reversible gates.Figure 1.3 Reversible Feynman gate.Figure 1.4 Quantum realization of reversible Fredkin (FRG) gate.Figure 1.5 The quantum representation of reversible HNG gate.Figure 1.6 Block diagram of the reversible FRG gate.Figure 1.7 Quantum representation of a reversible FRG gate.Figure 1.8 Toffoli gates as self‐reversible.Figure 1.9 Quantum cost calculation of Feynman gate.Figure 1.10 Quantum circuit of Toffoli gate.Figure 1.11 Quantum circuit of Fredkin gate.Figure 1.12 Quantum circuit of a Peres gate.

2 Chapter 2Figure 2.1 Multi‐operand n‐digit decimal adder.Figure 2.2 The architecture of reversible multi‐operand n‐digit decimal adde...Figure 2.3 The architecture of reversible single‐digit block of m‐operand n‐...Figure 2.4 4 4 reversible FAG gate.Figure 2.5 Reversibility of 4 4 reversible FAG gate.Figure 2.6 Reversible FAG gate as full adder.Figure 2.7 The n‐bit carry skip adder circuit.Figure 2.8 Single block carry skip adder circuit.Figure 2.9 Reversible CSA for single digit.Figure 2.10 Reversible carry skip circuit.Figure 2.11 Reversible partial full adder.Figure 2.12 n‐bit CLA adder circuit.Figure 2.13 A 1‐digit BCD adder's overflow detection logic.Figure 2.14 A 1‐bit BCD adder correction logic circuit.Figure 2.15 A 1‐digit BCD adder.Figure 2.16 A carry skip 1‐digit BCD adder.Figure 2.17 Nine's complement circuit.Figure 2.18 Modified nine's complement circuit.Figure 2.19 Modified conventional BCD subtractor.Figure 2.20 CLA BCD subtractor.Figure 2.21 Carry skip BCD subtractor.Figure 2.22 Reversible nine's complement.Figure 2.23 Reversible BCD subtractor.Figure 2.24 Reversible CLA BCD subtractor.Figure 2.25 Reversible logic implementation of the carry skip BCD adder.

3 Chapter 3Figure 3.1 Process of 4 4 multiplications.Figure 3.2 Block diagram of a reversible HNG gate.Figure 3.3 The quantum representation of a reversible HNG gate.Figure 3.4 Symbols of the controlled‐T and controlled‐ gate.Figure 3.5 5 5 BSJ gate and its corresponding input–output mapping.Figure 3.6 Quantum realization of 5 5 BSJ gate.Figure 3.7 3 3 MPG and its corresponding input–output mapping.Figure 3.8 Quantum realization of 3 3 MPG.Figure 3.9 Quantum analysis of 3 3 MPG.Figure 3.10 A compact quantum realization of 3 3 MPG.Figure 3.11 Block diagram of R cell.Figure 3.12 Construction of R cell.Figure 3.13 3 3 MTG and its corresponding input–output mapping.Figure 3.14 Quantum realization of 4 4 MTG.Figure 3.15 3 3 MFRG and its corresponding input–output mapping.Figure 3.16 Quantum realization of 4 4 MFRG.Figure 3.17 A Compact quantum realization of 4 4 MFRG.Figure 3.18 16 16 PPG array.Figure 3.19 Gate level diagram of a 4 4 PPG for reversible Booth's multipl...Figure 3.20 Block diagram of an PPG for reversible Booth's multiplier.Figure 3.21 Gate level diagram of a 4 4 MOA for reversible Booth's multipl...Figure 3.22 Diagram of an n n MOA for reversible Booth's Multiplier.Figure 3.23 (a) MOA (b) MOA.Figure 3.24 Critical path for an 8 8 PPG for reversible Booth's multiplier...Figure 3.25 Critical path for a 6 6 MOA for reversible Booth's multiplier....

4 Chapter 4Figure 4.1 Two‐input n‐bit reversible MUX.Figure 4.2 A clocked D Flip‐Flop.Figure 4.3 An n‐bit reversible D flop‐flop.Figure 4.4 Implementation of the characteristic function of Equation (4.2.3....Figure 4.5 The structure of the basic cell for the reversible PIPO left‐shif...Figure 4.6 The block diagram of the basic cell for the reversible PIPO left‐...Figure 4.7 An n‐bit reversible PIPO left‐shift register.Figure 4.8 An ‐bit parallel adder (carry‐out ignored).Figure 4.9 Illustration of the division circuit.

5 Chapter 5Figure 5.1 Reversible BJS gate.Figure 5.2 Quantum realization of the BJS gate.Figure 5.3 Reversible HLN gate.Figure 5.4 Quantum realization of the HLN gate.Figure 5.5 BJS gate works as reversible 1‐bit comparator.Figure 5.6 BJS gate works as reversible MSB comparator.Figure 5.7 The GE comparator cell.Figure 5.8 Block diagram of the single‐bit GE comparator cell.Figure 5.9 The LT comparator cell.Figure 5.10 Block diagram of the single‐bit LT comparator cell.Figure 5.11 Reversible 2‐bit comparator.Figure 5.12 Reversible n‐bit comparator.

6 Chapter 6Figure 6.1 Mapping of JK latch (Equation ) on the Fredkin gate.Figure 6.2 Mapping of variable (Equation J ) on the Fredkin gate.Figure 6.3 Reversible design of latch with minimal garbage outputs.Figure 6.4 Conventional cross‐coupled SR latch.Figure 6.5 Peres gate based SR latch without enable.Figure 6.6 Reversible SR latch based on modified truth table.Figure 6.7 Reversible gated SR latch based on modified truth table.Figure 6.8 Fredkin gate‐based D latch with one Feynman gate.Figure 6.9 Fredkin gate‐based D latch with two Feynman gates.Figure 6.10 Fredkin gate‐based negative enable reversible D latch with only ...Figure 6.11 Fredkin gate‐based negative enable reversible D latch with outpu...Figure 6.12 Peres gate‐based latch.Figure 6.13 Reversible T latch with outputs and .Figure 6.14 Reversible JK latch with outputs and .Figure 6.15 Reversible master–slave D flip‐flop.Figure 6.16 Reversible master–slave T flip‐flop.Figure 6.17 Reversible master–slave JK flip‐flop.Figure 6.18 Reversible master–slave SR flip‐flop.Figure 6.19 Application of the Fredkin gate to avoid the fan‐out.Figure 6.20 Asynchronous reset of the and outputs of the Fredkin gate.Figure 6.21 Asynchronous set of the and outputs of the Fredkin gate.Figure 6.22 Fredkin gate‐based asynchronous set/reset D latch.Figure 6.23 Reversible asynchronous set/reset master–slave D flip‐flop.

7 Chapter 7Figure 7.1 Reversible flip‐flop.Figure 7.2 Reversible clocked T flip‐flop for synchronous counter.Figure 7.3 Reversible clocked T flip‐flop for asynchronous counter.Figure 7.4 Block diagram of MPG gate.Figure 7.5 Quantum representation of 3 3 MPG gate.Figure 7.6 Reversible master–slave T flip‐flop.Figure 7.7 4‐bit reversible asynchronous counter.Figure 7.8 4‐bit reversible synchronous counter.Figure 7.9 Quantum implementation of a reversible 2–to–4 decoder.Figure 7.10 Measurement of the quantum delay for the reversible 2–to–4 decod...Figure 7.11 Reversible 2–to–4 decoder.Figure 7.12 Reversible 4–to–2 encoder.

8 Chapter 8Figure 8.1 Simple block diagram of the barrel shifter.Figure 8.2 Block diagram of the reversible MBJN gate.Figure 8.3 Quantum realization of the reversible MBJN gate.Figure 8.4 Reversible 2‐bit 2's complement generator.Figure 8.5 Reversible 3‐bit 2's complement generator.Figure 8.6 Reversible 3‐bit swap condition generator.Figure 8.7 Reversible 4‐bit swap condition generator.Figure 8.8 A (4, 3) reversible right rotator.Figure 8.9 Block diagram of (8, 7) reversible bidirectional barrel shifter....Figure 8.10 Structure of the reversible clocked D flip‐flop.Figure 8.11 Block diagram of the reversible clocked D flip‐flop.Figure 8.12 n‐bit reversible SISO shift register.Figure 8.13 n‐bit reversible SIPO shift register.Figure 8.14 n‐bit reversible PISO shift register.Figure 8.15 Implementation of the characteristic function of Equation (8.2.1...Figure 8.16 Basic cell for the reversible PIPO shift register.Figure 8.17 Block diagram for the reversible PIPO shift register.Figure 8.18 n‐bit reversible PIPO shift register.Figure 8.19 Implementation of the characteristic function of Equation (8.2.1...Figure 8.20 Basic cell for the reversible universal shift register.Figure 8.21 Block diagram for the reversible universal shift register.Figure 8.22 n‐bit reversible universal shift register.

9 Chapter 9Figure 9.1 Reversible gate 1 (RG1).Figure 9.2 Reversible gate 2 (RG2).Figure 9.3 Reversible R‐I gate.Figure 9.4 Transistor level realization of reversible R‐I gate.Figure 9.5 Realization of 2:1 multiplexer using reversible R‐I gate.Figure 9.6 Realization of 1:2 demultiplexer using reversible R‐I gate.Figure 9.7 Realization of two‐input XOR using reversible R‐I gate.Figure 9.8 Realization of two‐input AND gate using reversible R‐I gate.Figure 9.9 Reversible R‐II gate.Figure 9.10 Transistor level circuit for the reversible R‐II gate.Figure 9.11 Realization of 2:1 multiplexer using reversible R‐II gate.Figure 9.12 Realization of two‐input XOR and half adder using reversible R‐I...Figure 9.13 Realization of two‐input AND gate using reversible R‐II gate.

10 Chapter 10Figure 10.1 Block diagram of 3 3 reversible NH gate.Figure 10.2 Quantum realization of 3 3 reversible NH gate.Figure 10.3 Block diagram of 4 4 reversible BSP gate.Figure 10.4 4‐to‐1 reversible MUX.Figure 10.5 Reversible D latch.Figure 10.6 Reversible Write‐Enabled Master–Slave flip‐flop.Figure 10.7 Block diagram of a reversible RAM.Figure 10.8 A reversible logic element of Plessey FPGA.Figure 10.9 Reversible MUX gate.Figure 10.10 Different uses of a Feynman gate.Figure 10.11 One template of toffoli gate.Figure 10.12 Two templates of MUX gate.Figure 10.13 Ex‐OR plane realization for the function F based on the Algorit...Figure 10.14 Design of reversible PLAs for multi‐output function F.Figure 10.15 Delay calculation of AND plane: (a‐b) delay propagation path of...Figure 10.16 Delay calculation of Ex‐OR plane: (a‐b) delay propagation path ...

11 Chapter 11Figure 11.1 Block diagram of reversible FS gate.Figure 11.2 Quantum realization of reversible FS gate.Figure 11.3 Reversible decoder.Figure 11.4 3 2 Reversible decoder.Figure 11.5 n reversible decoder.Figure 11.6 Reversible D flip‐flop.Figure 11.7 Reversible write‐enabled master–slave D flip flop.Figure 11.8 Reversible RAM.Figure 11.9 Reversible ITS decoder.Figure 11.10 Quantum representation of reversible ITS decoder.Figure 11.11 Block diagram of reversible PROM.Figure 11.12 Reversible TI gate.Figure 11.13 Different uses of Feynman gate.Figure 11.14 Template of Toffoli gate.Figure 11.15 Two templates of TI gate.Figure 11.16 The combined design of AND plane and Ex‐OR plane.

12 Chapter 12Figure 12.1 Logic diagram of a conventional ALU.Figure 12.2 The reversible function generator.Figure 12.3 Block diagram of reversible function generator.Figure 12.4 The reversible control unit.Figure 12.5 Block diagram of the reversible control unit.Figure 12.6 The design of 16‐bit reversible ALU.

13 Chapter 13Figure 13.1 Block diagram of a 16‐bit control unit.Figure 13.2 Block diagram of reversible HL gate.Figure 13.3 Quantum realization of reversible HL gate.Figure 13.4 Block diagram of reversible BJ gate.Figure 13.5 NAND implementation of reversible BJ gate.Figure 13.6 2‐to‐4 Reversible decoder using FG and FRG gate.Figure 13.7 2‐to‐4 Reversible decoder using HL gate.Figure 13.8 Reversible 3‐to‐8 decoder (Approach 1).Figure 13.9 Reversible 3‐to‐8 decoder (Approach 2).Figure 13.10 Reversible ‐to‐ decoder (Approach 1).Figure 13.11 Reversible ‐to‐ decoder (Approach 2).Figure 13.12 Reversible JK flip flop.Figure 13.13 4‐bit reversible sequence counter.Figure 13.14 16‐bit reversible instruction register.Figure 13.15 Reversible control gates associated with AR.

14 Chapter 14Figure 14.1 Feynman double gate.Figure 14.2 Feynman double gate preserves fault tolerance over input–output ...Figure 14.3 Fredkin gate.Figure 14.4 New fault‐tolerant gate.Figure 14.5 Parity‐preserving HC gate.Figure 14.6 Parity‐preserving IG gate.Figure 14.7 Parity‐preserving IG gate as a NOT gate.Figure 14.8 Parity‐preserving IG gate as AND gate and Ex‐OR gate.Figure 14.9 Parity‐preserving IG gate as Ex‐OR gate, Ex‐NOR gate and OR gate...Figure 14.10 Quantum representation of NFT gate.Figure 14.11 Design of single NFT full adder.Figure 14.12 Design of fault‐tolerant CSA.Figure 14.13 Design of 4‐bit fault‐tolerant CLA.Figure 14.14 FTFA circuit.Figure 14.15 Fault‐tolerant ripple carry adder.

15 Chapter 15Figure 15.1 Working procedure of a multiplier circuit.Figure 15.2 Reversible LMH gate.Figure 15.3 Quantum realization of LMH gate.Figure 15.4 Partial product generator circuit.Figure 15.5 Generalized architecture of fault‐tolerant PPG.Figure 15.6 multi‐operand addition circuit.Figure 15.7 Generalized architecture of fault‐tolerant MOA.

16 Chapter 16Figure 16.1 Illustration of the decomposition of a binary number.Figure 16.2 Example of a division operation.Figure 16.3 2‐input ‐bit reversible fault‐tolerant MUX.Figure 16.4 Block diagram of RR gate.Figure 16.5 Reversible fault‐tolerant D latch using RR gate.Figure 16.6 Block diagram of F2PG gate.Figure 16.7 Reversible fault‐tolerant PIPO left‐shift register.Figure 16.8 Reversible fault‐tolerant register.Figure 16.9 Reversible fault‐tolerant rounding register.Figure 16.10 Reversible fault‐tolerant normalization register.Figure 16.11 Reversible fault‐tolerant NFTFAG.Figure 16.12 Quantum representation of NFTFAG.Figure 16.13 NFTFAG as a reversible fault‐tolerant full adder.Figure 16.14 ‐bit reversible fault‐tolerant parallel adder.Figure 16.15 ‐bit reversible fault‐tolerant parallel adder.Figure 16.16 Block diagram of the 2‐bit reversible fault‐tolerant division c...

17 Chapter 17Figure 17.1 Block diagram of F2G.Figure 17.2 Quantum equivalent realization of F2G.Figure 17.3 Transistor realization of F2G.Figure 17.4 Block diagram of FRG.Figure 17.5 Quantum equivalent realization of FRG.Figure 17.6 Transistor realization of FRG.Figure 17.7 ‐to‐ Reversible fault‐tolerant decoder.Figure 17.8 Block diagram of the ‐to‐ RFD.Figure 17.9 Block diagram of the ‐to‐ RFD.Figure 17.10 Schematic diagram of the ‐to‐ RFD.Figure 17.11 Block diagram of the ‐to‐ decoder.Figure 17.12 Combinations of the two quantum primitive gates.

18 Chapter 18Figure 18.1 Adaptive structure of (n, k) logarithmic barrel shifter.Figure 18.2 (4, 2) Reversible fault‐tolerant unidirectional logarithmic barr...Figure 18.3 (8, 3) Reversible fault‐tolerant unidirectional logarithmic barr...Figure 18.4 Reversible fault‐tolerant unidirectional logarithmic right rot...Figure 18.5 (4, 2) Reversible fault‐tolerant unidirectional logarithmic logi...Figure 18.6 (8,3) Reversible fault‐tolerant unidirectional logarithmic logic...Figure 18.7 (n,k) reversible fault‐tolerant logarithmic logical shifter (cir...

19 Chapter 19Figure 19.1 AND Ex‐OR programmable logic array.Figure 19.2 Four different orientations.Figure 19.3 Realization of multi‐output function (F) based on Algorithm 19.1...Figure 19.4 Realization of multi‐output function based on Algorithm 19.1.1...Figure 19.5 Different representations of Fredkin gate.Figure 19.6 The design of AND plane of reversible fault‐tolerant PAL.Figure 19.7 Feynman extension gate (FEG).Figure 19.8 The design of the Ex‐OR plane of a reversible fault‐tolerant PAL...Figure 19.9 The block diagram of reversible fault‐tolerant MSH gate.Figure 19.10 The quantum realization of reversible fault‐tolerant MSH gate w...Figure 19.11 The block diagram of reversible fault‐tolerant MSB gate.Figure 19.12 The quantum realization of reversible fault‐tolerant MSB gate w...Figure 19.13 The transistor realization of reversible fault‐tolerant MSH gat...Figure 19.14 The transistor realization of reversible fault‐tolerant MSB gat...Figure 19.15 The block diagram of reversible fault‐tolerant D latch.Figure 19.16 The block diagram of reversible fault‐tolerant master–slave fli...Figure 19.17 The block diagram of a reversible fault–tolerant 4 1 multiple...Figure 19.18 The block diagram of reversible fault‐tolerant three‐input LUT....Figure 19.19 The block diagram of reversible fault‐tolerant four‐input LUT....Figure 19.20 The block diagram of reversible fault‐tolerant CLB of FPGA.

20 Chapter 20Figure 20.1 Reversible fault‐tolerant UPPG gate.Figure 20.2 Quantum realization of LMH gate.Figure 20.3 Circuit structure of Group‐1 PP cell.Figure 20.4 Compressed block diagram of Group‐1 PP cell.Figure 20.5 Block diagram of Group‐2 PP (Cell) .Figure 20.6 Block diagram of Group‐2 PP cell.Figure 20.7 Block diagram of Group‐3 PP cell.Figure 20.8 Reversible fault‐tolerant 2‐bit ALU.Figure 20.9 n‐bit reversible fault‐tolerant ALU.

21 Chapter 21Figure 21.1 Reversible logic gate R1.Figure 21.2 Reversible logic gate R2.Figure 21.3 Reversible logic gate R3.Figure 21.4 Realizations of OR and Ex‐OR Gates Using R1 Gate.Figure 21.5 Realizations of Ex‐NOR and NAND gates using R1 gate.Figure 21.6 Realization of NOR gate using R1 gate.Figure 21.7 Realization of AND gate using R1 gate.Figure 21.8 The testable logic block using R1 and R2 gates.Figure 21.9 Two‐pair rail checker.Figure 21.10 Testable block embedded with two‐pair rail checker.Figure 21.11 Realization of NAND gate using R1 and R2 gates.Figure 21.12 Reversible NAND block implementation for the function ab + cd...Figure 21.13 Implementation of signal duplication.

22 Chapter 22Figure 22.1 Block diagram of R1 gate.Figure 22.2 Block diagram of R2 gate.Figure 22.3 Block diagram of R gate.Figure 22.4 Construction of a testable block (TB).Figure 22.5 Block diagram of a testable block (TB).Figure 22.6 Block diagram of UFT gate.Figure 22.7 Compact representation of a UFT gate.Figure 22.8 Quantum realization of a UFT circuit.Figure 22.9 AND and EX‐OR operations of UFT gate.Figure 22.10 OR operation of UFT gate.Figure 22.11 NAND and NOT operations of UFT gate.Figure 22.12 EX‐OR and EX‐NOR operations of UFT gate.Figure 22.13 NOR operation of the UFT gate.Figure 22.14 Nontestable circuit for .Figure 22.15 Online testable circuit for Example 22.2.2.1.Figure 22.16 Nontestable full adder using ESOP technique.Figure 22.17 Online testable full adder circuit.

23 Chapter 23Figure 23.1 Reversible computer dissipates less heat than a conventional com...Figure 23.2 Reversible computer has the same number of outputs and inputs.Figure 23.3 Working mechanism of a reversible computer.Figure 23.4 Reversible logic gates.Figure 23.5 Back‐up states of a reversible computing system.

24 Chapter 24Figure 24.1 Hydrogen bonds of the interior DNA.Figure 24.2 DNA structureFigure 24.3 Structure of DNA.Figure 24.4 Ligation process of DNA.Figure 24.5 HPP on seven vertices.Figure 24.6 DNA replication process.

25 Chapter 25Figure 25.1 Overview of the methodology.Figure 25.2 Part of the tree structure.Figure 25.3 Structure of a node.Figure 25.4 DNA sequence of a node for 20 nodes tree.Figure 25.5 DNA combination.

26 Chapter 26Figure 26.1 Operation of DNA‐based reversible NOT gate (DRNG).Figure 26.2 Operation of DNA‐based reversible Ex‐OR gate.Figure 26.3 Operation of DNA‐based reversible AND gate.Figure 26.4 Operation of DNA‐based reversible OR gate.Figure 26.5 Overall procedures of DNA hybridization for a DNA‐based Toffoli ...Figure 26.6 DNA‐based Toffoli gate as NOT gate.Figure 26.7 DNA‐based Toffoli gate as AND gate.Figure 26.8 DNA‐based Toffoli gate as OR gate.Figure 26.9 DNA‐based Toffoli gate as Ex‐OR gate.Figure 26.10 Procedures of DNA hybridization for DNA‐based Fredkin gate.Figure 26.11 DNA hybridization of selection operation between two ANDed prod...Figure 26.12 Gate‐level representation of reversible half‐adder using Toffol...Figure 26.13 Reversible DNA‐based half‐adder.

27 Chapter 27Figure 27.1 Gate‐level representation of a reversible full‐adder circuit.Figure 27.2 Operation of DNA‐based reversible full‐adder circuit.Figure 27.3 DNA‐based reversible adder/subtractor circuit.Figure 27.4 DNA hybridization of logical AND operation using DNA‐based Toffo...Figure 27.5 DNA hybridization of logical NOT operation using DNA‐based Toffo...Figure 27.6 DNA hybridization of logical AND operation between complemented ...Figure 27.7 DNA hybridization of logical Ex‐OR operation using DNA‐based Tof...Figure 27.8 DNA hybridization of selection operation using DNA‐based Fredkin...Figure 27.9 The working principle of DNA comparator.

28 Chapter 28Figure 28.1 Operation of DNA‐based reversible NOT gate.Figure 28.2 The four basic biochemical events of the shifter circuit.Figure 28.3 The working procedures of DNA‐based reversible multiplication op...Figure 28.4 An example of DNA‐based reversible multiplication operation.

29 Chapter 29Figure 29.1 Block diagram of DNA‐based reversible multiplexer circuit.Figure 29.2 DNA hybridization of the first Fredkin gate for selection operat...Figure 29.3 DNA hybridization of second Fredkin gate for selection operation...Figure 29.4 DNA hybridization of third Fredkin gate for selection operation....Figure 29.5 DNA hybridization of the fourth Fredkin gate for selection opera...Figure 29.6 DNA hybridization of the fifth Fredkin gate for selection operat...Figure 29.7 Diagram of DNA‐based reversible logic unit.Figure 29.8 Diagram of DNA‐based reversible logic unit.

30 Chapter 30Figure 30.1 Fredkin gate symbol and its working procedure as a conditional s...Figure 30.2 Forming dsDNA by hybridizing the two complementary ssDNA and for...Figure 30.3 a. A one‐to‐one mapping between binary bit and DNA strands with ...Figure 30.4 a. Fredkin gate with three inputs and three outputs. b. Simulati...Figure 30.5 a. The Fredkin gate with three inputs and three outputs and thre...Figure 30.6 a. The Fredkin gate with three inputs and three outputs. b. The ...Figure 30.7 a. The D latch based on Fredkin gate. b. The DNA D latch based o...Figure 30.8 DNA reversible master–slave D flip‐flop with the CP clock pulse,...

31 Chapter 31Figure 31.1 DNA double helix.Figure 31.2 DNA computer solving a shortest path problem.Figure 31.3 Traveling salesman problem.Figure 31.4 Parallel computing.Figure 31.5 Concept of DNA chips.Figure 31.6 Swarm intelligence in nature.Figure 31.7 Swarm intelligence in nature.Figure 31.8 Huge memory capacity of DNA.Figure 31.9 Low‐power DNA computers.