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Figure 1 presents MARS electronic system. It is based on desktop and VME modules from CAEN SpA:

– TwoA1422 charge sensitive preamplifiers. They present a sensitivity of 90 mV/MeV (for Si detectors) and support a detector capacitance up to 200 pF (F2 type). The A1422 are implemented into alloy boxes, 8 channels each, and feature BNC connectors for the input (detector), SHV for high voltage supply, LEMO for the energy output and the input test (TEST IN), and a cable with a D – type 9 pin male connector for the power supply [17].

– The DT5423 power distributor provides 4 standard D-type 9 pin fe male connectors to supply up to 4 A1422 preamplifiers with ± 12 V [18].

An alternative VME form factor module [19] could be employed and inte grated in the same VME crate described below.

– Three V6519P HV power supply modules provide the high voltage (up to 500 V and 3 mA of voltage and current, respectively) to the de tectors. Each one houses 6 HV power supply channels that are controlled by software. The channels share a common floating return which allows on-detector grounding, reducing the noise level. HV outputs are delivered by SHV connectors [20].– The V1725S digitizer consists of 16 (0—15) input channels capable of recording waveforms (directly from the preamplifiers A1422 [17]) along with performing advanced algorithms for online DPP [21]. Using DPP f irmware, we are able to acquire the integrated charge and carry out PSD (Pulse Shape Discrimination) and PHA (Pulse Height Analysis), as well as read out waveforms with automatic pulse identification. It features 14 bit resolution, 250 MS/s sampling rate, and 2 V input range. This implies a digital precision of 0.12 mV and a digital resolution of 0.006%, with a processing time of 65 µs. Communication with the board can be done through the VME bus and Optical Link. It is well suited for mid fast pulses such as the ones coming from silicon detectors coupled to the charge sensitive preamplifiers A1422 [17].

– The V1718 bridge is a VMEtoUSB2.0 bridge. It acts as a VME master module and can be operated from a USB port of a standard PC [22].

– The VME8008Bisan8slotVME cratesuitable for 6U x 160 mmboards, which serves as a support and power supply for the electronic modules V6519P, V1725S, and V1718 [23].

2.3. MARS acquisition system

The V1725S digitizer runs the DPP-PSD/PHA firmware. The digitizer im plements a digital replacement of discriminator, pulse shaping, and gate gener ator. These functions are performed inside the FPGA (onboard) without using external cables, delay lines and/or other boards. The V1725S digitizer itself con sists of a multi-channel data acquisition system that replaces traditional analog boards and constitutes a single compact tool for nuclear reactions spectroscopy. A PC with an Intel i7 (1.8 GHz, 8 CPUs) and 16 GB RAM handles the data acquisition by means of CoMPASS (CAEN Multi-PArameter Spectroscopy Software) [24]. CoMPASS represents the GUI, manages parameters, builds plots and saves the energy and time spectra. Within CoMPASS, we can set discriminator parameters such as: threshold, discrimination type, and trigger holdoff. In addition, we can set parameters related to PHA: trapezoid rise time, flat top, pole-zero; parameters related to PSD: pre-gate, short gate and long gate; as well as the gain and the number of channels of the spectra. It also allows to discard pile-up and saturation events besides applying energy, time, and PSD filters.

(a) PSD firmware. The input signal (black) within the long and short gates (red and green squared pulses). At the bottom, we have the constant fraction discriminator (CFD) signal (blue). (b) PHA firmware. The input signal (black with long tail), the fast trigger (left red), and the trapezoid filter (blue) with the peaking signal (green) just below the trapezoid. Figure 2: CoMPASS screenshots showing different electronic signals for (a) PSD firmware, and (b) PHA firmware.

Moreover, the V1725S digitizer has a logic unit that allows for measuring coincidences. Through CoMPASS, we are able to acquire events in logic AND between pairs of consecutive data acquisition chains (ch0 & ch1 || ch2 & ch3 || and so on). For this, a coincidence (time) window must be enabled and defined. Once the first detector is triggered, any signal triggering the second detector, within the specified time window, will validate an event (in coincidence). Anti coincidences can also be performed using external logic modules and using the generated gate as an input to the digitizer trigger input.