Читать книгу Design for Excellence in Electronics Manufacturing - Cheryl Tulkoff - Страница 2
ОглавлениеTable of Contents
1 Cover
2 Series Title Wiley Series in Quality & Reliability Engineering Wiley Series in Quality & Reliability Engineering
9 Series Editor's Foreword by Dr. Andre Kleyner
10 Foreword
11 Preface
13 Acronyms
14 1 Introduction to Design for Excellence 1.1 Design for Excellence (DfX) in Electronics Manufacturing 1.2 Chapter 2: Establishing a Reliability Program 1.3 Chapter 3: Design for Reliability (DfR) 1.4 Chapter 4: Design for the Use Environment: Reliability Testing and Test Plan Development 1.5 Chapter 5: Design for Manufacturability (DfM) 1.6 Chapter 6: Design for Sustainability 1.7 Chapter 7: Root Cause Problem‐Solving, Failure Analysis, and Continual Improvement Techniques
15 2 Establishing a Reliability Program 2.1 Introduction 2.2 Best Practices and the Economics of a Reliability Program 2.3 Elements of a Reliability Program 2.4 Reliability Data 2.5 Analyzing Reliability Data: Commonly Used Probability and Statistics Concepts in Reliability 2.6 Reliability Analysis and Prediction Methods 2.7 Summary References
16 3 Design for Reliability 3.1 Introduction 3.2 DfR and Physics of Failure 3.3 Specifications (Product and Environment Definitions and Concerns) 3.4 Reliability Physics Analysis 3.5 Surviving the Heat Wave 3.6 Redundancy 3.7 Plating Materials: Tin Whiskers 3.8 Derating and Uprating 3.9 Reliability of New Packaging Technologies 3.10 Printed Circuit Boards 3.11 Non‐Functional Pads 3.12 Wearout Mechanisms 3.13 Conformal Coating and Potting References
17 4 Design for the Use Environment: Reliability Testing and Test Plan Development 4.1 Introduction 4.2 Standards and Measurements 4.3 Failure‐Inducing Stressors 4.4 Common Test Types 4.5 Test Plan Development References
18 5 Design for Manufacturability 5.1 Introduction 5.2 Overview of Industry Standard Organizations 5.3 Overview of DfM Processes 5.4 Component Topics 5.5 Printed Circuit Board Topics 5.6 Process Materials 5.7 Summary: Implementing DfM References
19 6 Design for Sustainability 6.1 Introduction 6.2 Obsolescence Management 6.3 Long‐Term Storage 6.4 Long‐Term Reliability Issues 6.5 Counterfeit Prevention and Detection Strategies 6.6 Supplier Selection References
20 7 Root Cause Problem‐Solving, Failure Analysis, and Continual Improvement Techniques 7.1 Introduction 7.2 Root Cause Failure Analysis Methodology 7.3 Failure Reporting, Analysis, and Corrective Action System (FRACAS) 7.4 Failure Analysis 7.5 Continuing Education and Improvement Activities 7.6 Summary: Implementing Root Cause Methodology References
21 8 Conclusion to Design for Excellence: Bringing It All Together 8.1 Design for Excellence (DfX) in Electronics Manufacturing 8.2 Chapter 2: Establishing a Reliability Program 8.3 Chapter 3: Design for Reliability (DfR) 8.4 Chapter 4: Design for the Use Environment: Reliability Testing and Test Plan Development 8.5 Chapter 5: Design for Manufacturability 8.6 Chapter 6: Design for Sustainability 8.7 Chapter 7: Root Cause Problem Solving, Failure Analysis, and Continual Improvement Techniques
List of Tables
1 Chapter 2Table 2.1 Common quality and reliability issues.
2 Chapter 3Table 3.1 Diurnal temperature for Phoenix, Arizona.Table 3.2 Lead‐free HASL challenges.Table 3.3 Laminate material selection.Table 3.4 ECM risk guidelines.Table 3.5 Deliquescence characteristics.Table 3.6 Contaminant cleanliness limits.Table 3.7 Conformal coating selection.Table 3.8 Potting definitions.
3 Chapter 4Table 4.1 Climate in Death Valley, CA.Table 4.2 MIL‐STD‐810 vibration environments.Table 4.3 Product environment conditions.
4 Chapter 5Table 5.1 MSL levels.Table 5.2 Copper weight.Table 5.3 Sources of contaminants.Table 5.4 Soldering process DPMM.
5 Chapter 6Table 6.1 Storage Options Summary.Table 6.2 Failure modes of stored electronic components.Table 6.3 Counterfeit risk and cost.
6 Chapter 7Table 7.1 RCA method effort comparison.
List of Illustrations
1 Chapter 2Figure 2.1 Reliability tools across the design and development process.Figure 2.2 Block diagram for a simple fuel system.Figure 2.3 Parallel brake system.
2 Chapter 3Figure 3.1 Costs committed vs. money spent.Figure 3.2 Concurrent engineering flow.Figure 3.3 Reliability physics in the design phase.Figure 3.4 Classic bathtub curve.Figure 3.5 Capacitor susceptibility to wearout and breakdown.Figure 3.6 Variation in shipping container temperature.Figure 3.7 Reliability physics models.Figure 3.8 Hardware design process.Figure 3.9 Hardware design process feedback loop.Figure 3.10 Deep integration with existing simulation workflows.Figure 3.11 Initial parts placement.Figure 3.12 Thermal data.Figure 3.13 Out‐of‐plane displacement.Figure 3.14 Part selection: BOM creation flow.Figure 3.15 ESD entry vectors.Figure 3.16 Expansion and contraction behavior.Figure 3.17 Images of solder coarsening.Figure 3.18 Tin whiskers.Figure 3.19 Tin whisker intermetallic formation.Figure 3.20 Detailed geometry and mesh of traces and vias.Figure 3.21 Detailed view of high‐ and low‐stress pads.Figure 3.22 Immersion silver galvanic etching.Figure 3.23 Champagne voiding.Figure 3.24 Creep corrosion.Figure 3.25 Compression on a PTH from ICT.Figure 3.26 PTH barrel crack.Figure 3.27 Conductive anodic filament formation.Figure 3.28 Conductive anodic filament example.Figure 3.29 Hollow fiber example.Figure 3.30 Strain level from a 50 G mechanical shock.Figure 3.31 Example of excessive strain.Figure 3.32 Reduced strain after mount points are added.Figure 3.33 Corner staking, edge bonding, and underfill.Figure 3.34 Pad cratering cross section.Figure 3.35 Examples: dendrite (top) and CAF (bottom).Figure 3.36 Electrodissolution.Figure 3.37 E‐Field and dendritic growth.Figure 3.38 Non‐functional pads example.Figure 3.39 Typical bathtub curve.Figure 3.40 Conformal coating Tg behavior.
3 Chapter 4Figure 4.1 Changes to the typical bathtub curve.Figure 4.2 MLCC life expectancy.Figure 4.3 Temperature variation in a trucking container.Figure 4.4 Failure load conditions.Figure 4.5 Power cycling.Figure 4.6 Manufacturing operations impacting bending.Figure 4.7 Cracked capacitor and pad cratering.Figure 4.8 Strain gauge.Figure 4.9 Vibration durability issue 1.Figure 4.10 Vibration durability issue 2.Figure 4.11 Preconditioning Weibull slope change.Figure 4.12 Acceleration factor calculations.Figure 4.13 Potential failure modes and tests.
4 Chapter 5Figure 5.1 Cost increases associated with DfM implementation.Figure 5.2 IPC Standards 2019.Figure 5.3 Thermal stress crack.Figure 5.4 Visible thermal stress crack..Figure 5.5 Vertical crack under termination..Figure 5.6 Mechanical shock failure modes..Figure 5.7 ICT fixture.Figure 5.8 Resistor damaged by sulfur dioxide..Figure 5.9 IC wearout concern.Figure 5.10 Surface finishes.Figure 5.11 Black pad images.Figure 5.12 Silver creep..Figure 5.13 PTH failure..Figure 5.14 CAF examples..Figure 5.15 QFN bondline.Figure 5.16 QFN I/O pad and thin bondline.Figure 5.17 Windowpane stencil structure.Figure 5.18 Solder paste volume change..Figure 5.19 CTE and modulus change.Figure 5.20 Cleaning process considerations.
5 Chapter 6Figure 6.1 Kirkendall or champagne voids.Figure 6.2 Counterfeit definitions.Figure 6.3 Basic validation process flow.Figure 6.4 Plating voids.Figure 6.5 Glass fiber protrusion.Figure 6.6 Plating folds.Figure 6.7 Plating nodules.Figure 6.8 Etch pits.
6 Chapter 7Figure 7.1 Problem‐solving vs. root cause problem‐solving.Figure 7.2 The eight disciplines process.Figure 7.3 Scanning acoustic microscopy system.Figure 7.4 Through transmission acoustic microscopy.Figure 7.5 Peak amplitude acoustic microscopy.Figure 7.6 Phase inversion acoustic microscopy.Figure 7.7 X‐ray microscopy.Figure 7.8 Thermal imaging.Figure 7.9 Superconducting quantum interfering device microscopy.Figure 7.10 Decapsulation system.Figure 7.11 Cross‐section polishing.Figure 7.12 Cross‐section of a BGA.Figure 7.13 Scanning electron microscope system.Figure 7.14 SEM EDX spectra.Figure 7.15 Xyztec combination wire bond and shear tester.Figure 7.16 Fourier transform system.Figure 7.17 Ion chromatography system.Figure 7.18 Digital image correlation setup.Figure 7.19 Plan‐do‐check‐act process.
