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1.1 Introduction
ОглавлениеThe last century has witnessed the growth of physics and technology to a new height. In 1930, J. E. Lilienfield invented and filed a patent [1] for a new device structure called MOSFET that later became an integral part of modern technology. In addition, in the field of material science, the innovation of silicon (Si) as semiconductor material opened a new field of research where the conductivity of a material can be varied according to the requirement. Particularly from the late 1940s, several researchers started publishing various theoretical research findings in this new domain of physics. From the early 1960s, the fabrication of MOSFET started, and technological development has grown very rapidly since then.
In 1965, Gordon Moore proposed his famous prediction on future technological progress that the number of transistors in an Integrated Circuit (IC) will double in every 18 months [2] and this law was followed by the industry for a long time by gradually reducing the dimensions of the transistor. However, as the physics of planner Si MOSFET operation started approaching its fundamental limit in reduced dimensions, scientists started looking for alternatives to dimensional reductions to sustain the technological growth. In this regard, several new semiconductor materials (e.g., GaAs, InGaAs, Graphene, MoS2 etc.) are studied in place of Si to identify the possible alternative to it. In addition, various new device structures of transistor are also explored to overcome the challenges of MOSFET in such small-scaled dimensions. Among the new transistor structures, the FinFET device has been accepted by both academia and industry due to its several advantages over the other devices. Currently the latest processors are designed by leading companies by using FinFET devices to perform the high-speed operations with improved performance.
On the other hand, there are many scientists working on the performance improvement techniques such that the improved performance of lower dimensional structures can be achieved at higher dimensional devices and the challenges of lower dimensions can be avoided. Among these performance enhancement techniques, strain engineering has been emerging as the most feasible approach, and leading companies are using this technique currently to improve the performance of their transistors. However, there are many unknown areas in strain technology, and it needs to be explored further so that it can be used in new devices also.
In this chapter, gradual discoveries of strain engineering are discussed in brief for better understanding of how this performance enhancement technique has developed. In Section 1.2, theoretical analysis of strain engineering by various researchers is discussed. Strain affects various properties of material, like the band structure, conductivity, carrier mobility, etc., and how strain-induced changes modify the device parameters are calculated by several researchers and published in reputed journals and conferences. Some of these results are discussed in brief. In Section 1.3, different simulation studies on strain engineering are included. Various simulation data are compared with theoretical and experimental data to validate the simulation results, and future technological data are predicted by using the calibrated simulators. These simulations help to forecast the output of any new device or technique which is yet to be fabricated or implemented, and in this way the simulation process helps to continue future research without worrying about the fabrication cost and time. Due to these reasons, both scientists and fabrication companies are now depending upon the data shown by properly calibrated simulation software. In Section 1.4, various experimental results on strain engineering are shown and compared with theoretical and simulated data. In the last few decades, various scientists have explored strain engineered FET devices through several experiments and these results indicate that by using this performance enhancement technique, several challenges of unstrained nano-scale transistors can be overcome. Although there are not many laboratories to fabricate these modern FETs, many published reports are available to validate the theoretically and simulated predictions in this field of strain engineering. Some of these experimental data are discussed in brief to get some idea on real-time fabrication output. Finally, in Section 1.5, a summary of this chapter is discussed in brief and some possible future research problems in this area are included.