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Although the idea of strain technology first arrived in the 1950s [5–7], experimental implementation of strain engineering was performed in the 1980s [8, 9] when Si-SiGe hetero-junction devices were fabricated and change in carrier mobility and other parameters was analyzed. Later, in 1989, Harmand et al., studied the InAlAs/InGaAs hetero-junction growth on GaAs substrate and observed that the mismatch of lattice constants at the interface of different materials generate significant amount of stress and the carrier transport improves [31]. A major finding was observed by A. Hamada et al. [32], where the authors reported that in scaled MOSFET, the high vertical stress causes compressive surface stress that results in electron trapping in SiO₂ gate dielectric medium and as a result, trap assisted gate tunneling leakage current increases. These results gave some important guidelines on the use of mechanical stress for enhancing transistor performance in sub-micron dimensions.

Now, the strain engineering in planner MOSFET structure started with substrate induced biaxial stress [4, 29]. Although several research works were done by various scientists using this biaxial stress, however, due to several challenges, discussed in the earlier section, Ito et al. have proposed a new idea of introducing uniaxial tensile stress in the channel by Nitride capping layer [33] to improve n- channel MOSFET performance. For p- channel devices, Gannavaram et al. demonstrated that SiGe stressor material embedded sourcedrain regions induce compressive stress in the channel [34], and improves hole mobility in the channel. The new technique of introducing compressive channel stress to improve p- channel device performance led the scientists to explore more in this field of work, and in 2003, Ghani et al. of Intel fabricated a 90nm technology node MOSFET device [12] and reported several advantages of this SiGe embedded source-drain technology. Since then, several research works have been published on this field [4, 13, 23, 29] and the studies show that the lattice mismatch at the interface of source/drain and channel induces uniaxial compressive stress in the channel region of transistors. In [13], the authors have compared the performance of both uniaxial and biaxial channel stress in p- channel device and reported that, unlike biaxial stress, uniaxial channel stress helps to improve the mobility of holes more at low strain - high vertical field condition.

The impact of uniaxial channel stress on SiGe embedded source-drain MOSFET device performance have been studied thoroughly by Fossum and Zhang [35] and reported that threshold voltage shift is almost 5× smaller when compared to unstrained devices and device speed increases almost 16% due to the induced uniaxial stress in the CMOS ring oscillator. In [36], Thompson et al. studied the strain induced mobility enhancement in planner MOSFET for both holes and electron by theoretical modeling and experimentally measurement. It has been observed that due to uniaxial stress, maximum mobility enhancement is found to be greater than 4× and 1.7× for holes and electrons respectively.

The impact of strain engineering in non-volatile memory devices has been studied by Arghavani et al. [37] and it has been observed that the retention time is improved by tensile stress in n- channel devices, and degrades by the compressive stress in p- channel devices. The tensile stress improves the retention time due to change in barrier height at Si-SiO₂ and conductivity effective mass.

Various scientists are exploring the possible alternative of Si material in the channel region, and Xuan et al. [38] have reported that III-V compound semiconductor InGaAs could be the material with high mobility and improve performance. Furthermore, Yokoyama et al. [39] have shown that by introducing lateral strain in these III-V n- MOSFETs, performance can be improved further. However, for p- channel devices, T. J. Drummond et al. [40] have reported that biaxial stress needs to be applied in these InGaAs based quantum well devices to improve the hole mobility. There are many other reports available where several studies are performed on strained III-V materials for possible usage as nanowire transistors, and it has been found that by modulating the strain at core and shell regions, these materials can be used for these modern FETs [41, 42]. Thus, the compatibility of strain engineering in III-V compound semiconductors are becoming an alternative for Group-IV materials for various high-speed applications in coming days.

On the other hand, few researchers are also exploring thin films to generate a large amount of stress by the crystalline mismatch at substrate-thin film interface. Gilardi et al. [43] have shown the real-time monitoring of stress generation during the growth of thin films and presented a new measurement technique to measure the substrate curvature in strain engineering. There are other scientists exploring the possibilities of strain engineering in nanowire FETs. Li Song et al. [44] have explored the impact of strain engineering in Si nanowire and found that when ultra-large (> 10%) strain is applied along <100> direction, the Si keeps an indirect band gap; however, when the strain is applied along <110> and <111> direction, it becomes direct band gap semiconductor. These results provide a significant insight of strain engineering in Si nanowire applications.