Читать книгу Multi-Processor System-on-Chip 2 - Liliana Andrade - Страница 2

1  Cover

2  Title Page

3  Copyright

4  Foreword

5  Acknowledgments

6  PART 1: MPSoC for Telecom 1 From Challenges to Hardware Requirements for Wireless Communications Reaching 6G 1.1. Introduction 1.2. Breadth of workloads 1.3. GFDM algorithm breakdown 1.4. Algorithm precision requirements and considerations 1.5. Implementation 1.6. Conclusion 1.7. Acknowledgments 1.8. References 2 Towards Tbit/s Wireless Communication Baseband Processing: When Shannon meets Moore 2.1. Introduction 2.2. Role of microelectronics 2.3. Towards 1 Tbit/s throughput decoders 2.4. Conclusion 2.5. Acknowledgments 2.6. References

7  PART 2: Application-specific MPSoC Architectures 3 Automation for Industry 4.0 by using Secure LoRaWAN Edge Gateways 3.1. Introduction 3.2. Security in IIoT 3.3. LoRaWAN security in IIoT 3.4. Threat model 3.5. Trusted boot chain with STM32MP1 3.6. LoRaWAN gateway with STM32MP1 3.7. Discussion and future scope 3.8. Acknowledgments 3.9. References 4 Accelerating Virtualized Distributed NVMe Storage in Hardware 4.1. Introduction 4.2. Motivation: NVMe storage for the cloud 4.3. Design 4.4. Implementation 4.5. Results 4.6. Conclusion 4.7. References 5 Modular and Open Platform for Future Automotive Computing Environment 5.1. Introduction 5.2. Outline of this approach 5.3. Results 5.4. Use case 5.5. Conclusion 5.6. References 6 Post-Moore Datacenter Server Architecture 6.1. Introduction 6.2. Background: today’s blades are from the desktops of the 1980s 6.3. Memory-centric server design 6.4. Data management accelerators 6.5. Integrated network controllers 6.6. References

8  PART 3: Architecture Examples and Tools for MPSoC 7 SESAM: A Comprehensive Framework for Cyber–Physical System Prototyping 7.1. Introduction 7.2. An overview of the SESAM platform 7.3. VPSim: fast and easy virtual prototyping 7.4. Hybrid prototyping 7.5. FMI for co-simulation 7.6. Conclusion 7.7. References 8 StaccatoLab: A Programming and Execution Model for Large-scale Dataflow Computing 8.1. Introduction 8.2. Static dataflow 8.3. Dynamic dataflow 8.4. Dataflow execution models 8.5. StaccatoLab 8.6. Large-scale dataflow computing? 8.7. Acknowledgments 8.8. References 9 Smart Cameras and MPSoCs 9.1. Introduction 9.2. Early VLSI video processors 9.3. Video signal processors 9.4. Accelerators 9.5. From VSP to MPSoC 9.6. Graphics processing units 9.7. Neural networks and tensor processing units 9.8. Conclusion 9.9. References 10 Software Compilation and Optimization Techniques for Heterogeneous Multi-core Platforms 10.1. Introduction 10.2. Dataflow modeling 10.3. Source-to-source-based compiler infrastructure 10.4. Software distribution 10.5. Results 10.6. Conclusion 10.7. References

9  List of Authors

10  Author Biographies

11  Index

12  End User License Agreement