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Frame 1.4

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Figure 1.3 illustrates the internal architecture for a Mealy FSM.


Figure 1.3 Block diagram of a Mealy state machine structure.

Note the feed forward paths between the outside world inputs and the input to the output decoder.

The figure shows that the FSM has a number of inputs that connect to the next state decoder (combinational) logic. The Q outputs of the memory element flip‐flops connect to the output decoder logic, which in turn connects to the outside world outputs via the output decoder.

The flip‐flop outputs are used as next state inputs to the next state decoder, and it is these that determine the next state that the FSM will move to. Once the FSM has moved to this next state, its flip‐flops acquire a new present state as dictated by the next state decoder.

Note that some of the outside world inputs connect directly to the output decoder logic. This is the main feature of the Mealy type of FSM. This affects the outputs of the FSM.

Please turn to Frame 1.5.

Digital System Design using FSMs

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