Читать книгу Digital System Design using FSMs - Peter D. Minns - Страница 9
Оглавление
Preface
This book is, in large part, a development of FSM‐Based Digital Design using Verilog HDL (Minns and Elliott 2008), a book I wrote with Ian Elliott. It is rather unusual in that it forms a linear programmed learning text in all chapters to help readers learn on their own.
The intention in this current version is to make use of programmed learning methods in which the chapters are made up of frames that must be read in a sequential manner. It is hoped that the book will help readers in their study of the material. There is also new content in Chapter 6, Appendix A5, and Appendix A6, as well as consideration of unused states in finite state machines (FSMs).
It is assumed that the reader has a good understanding of Verilog HDL; however, the interested reader will find that Chapters 6, 7, and 8 of Minns and Elliott (2008) provide a very good account of Verilog HDL. Wiley make it possible to purchase these chapters on request for a small fee.
Note that in this version of the book the reader is given help to assist them as they progress through this book.
Indeed, Chapters 3, 4, 5, and 7 as well as some of the appendices include examples of FSMs with Verilog HDL for illustrated examples. Use is also made of the Digital logic simulation program Logisim to help the reader become familiar with using FSMs in the development of their work. This Logisim Simulator is freely available throughout the world to run on Windows, OS X, and Linux Operating Systems (see Appendix A2 for details).
The chapters are organized as follows.
Chapter 1 covers the introductory ideas of what FSMs are and how to represent them using a state diagram.
Chapter 2 covers the use of external devices and how to control them with an FSM.
Chapter 3 looks at how to synthesize FSMs using T type flip‐flops, then D type flip‐flops.
Chapter 4 introduces asynchronous FSM design.
Chapter 5 looks at the use of the one hot method of synchronous FSM design applied to clocked FSM designs.
Chapter 6, a new chapter, looks at applying an FSM to event‐driven systems, and considers one hot ideas and the one hot method.
Chapter 7 deals with Petri nets and how they can be used to synthesize electronic circuits using both sequential and parallel state machine design. This allows FSM‐based systems to support both sequential and parallel structures.
There are six appendices covering the necessary aspects of FSM systems that the reader needs to understand in the support of the FSM work. These are written in a more formal manner (i.e. not using frame method or programmed learning).
Appendix A1 looks at the logic gates and Boolean algebra used in this book. This should help those readers who may not have done much work on Boolean algebra for some time.
Appendix A2 is a tutorial on how to use the simulation programs and the Verilog Hardware Descriptive Language (HDL) with the SynaptiCAD system as well as a short introduction on the use of the gate logic simulator Logisim.
Appendix A3 covers the use of counters and shift registers as used in a number of the tutorials in this book. The reader should find them very useful.
Appendix A4 covers the use of behavioural Verilog HDL with some examples to help the reader become familiar with its use in the design of FSM‐based systems.
Appendix A5 looks at the way an FSM can be designed using digital hardware that can be programmed to produce programmable FSM systems. Tutorial examples are introduced to illustrate how this works.
Appendix A6 looks at how a rotation direction indicator can be implemented using an event‐driven FSM.
This book provides enough information for the reader to learn how to design their own FSMs and simulate them using the hardware descriptive language Verilog HDL.
I hope that the content of this book is both interesting and useful, and that it helps readers to learn more about digital system design using FSMs. I have used these techniques for many years, in lectures and when working with companies, and have found them really helpful.
Peter Minns BSc(h) PhD CENG MIET (retired)
Access to Wiley Web for my Verilog HDL and Logisim files:
