Читать книгу Digital System Design using FSMs - Peter D. Minns - Страница 21

If we look at the Moore FSM architecture again and remove all of the outside world inputs apart from the clock, and we also remove the output decoding logic, we are left with a very familiar architecture. This is shown in Figure 1.5.

Figure 1.5 Block diagram of a Class C state machine structure.

This architecture is in fact the synchronous counter the reader may have already seen in previous studies. Note that an up/down counter would have the additional outside world input ‘up/down’, which would be used to control the direction of counting.

The flip‐flop outputs in this architecture are used to connect directly to the outside world.

Please move on to Frame 1.8.