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Design of Low Power Junction-Less Double-Gate MOSFET

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Namrata Mendiratta and Suman Lata Tripathi*

VLSI Design Laboratory, Lovely Professional University, Phagwara, Punjab, India

Abstract

The requirement of low power consumption and higher IC packing density leads the designer to explore new MOSFET architectures with low leakage current and operating voltages. Multi-gate MOSFET architectures are a promising candidate with increased gate-control over the channel region. Double-gate MOSFET is one of the advanced MOSFETs with a thin-channel region sandwiched into the top and bottom gate. The changes in the position of the top and bottom gate overlap and also have a significant effect on the electrical characteristics of transistors. The higher number of gates increases the drive current capability of the transistor with enhanced gate control that is desired for low-power and high-speed operations of digital circuit and bulk memories. The junction-less feature future improves switching characteristics of multi-gate MOSFETs with more drive current and high ION/IOFF current ratio. These prefabrication low-power design and analysis can be done on a Visual TCAD device simulator with graphical and programming interfaces that reduce fabrication cost and improve overall throughput.

Keywords: Low power, junction-less, DGMOSFET, TCAD, leakage current, etc.

Design and Development of Efficient Energy Systems

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