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An AJ-DGMOSFET shown in Figure 1.1 has top and bottom gates arranged asymmetrically with an overlap region of 10nm. An n+ pocket region is added to the source side with heavy doping of donor atoms. p+ polysilicon is used as gate contact material with Hfas an oxide region of high-k dielectric constant. The body thickness is kept very low (6nm). The gate (L_gate) is 20 nm, with overlap region (L_overlap) of 10 nm. The body thickness (T_silicon) is 6 nm source /drain length (L_source = L_drain) of 8 nm. The oxide thickness (T_oxide) is 1 nm. A thin pocket region (n+ doping) is doped with 1x10²² cm^-3 with channel region II doping (n+ doping) of 1x10¹⁹ cm^-3. Including channel region I + and channel region II, the overall channel length becomes 30 nm.

The high doping concentration of the source drain region with heavy doping of n+ pocket region improves the ON-state current transistor. The drain region doping is slightly less than the source to achieve a low value of leakage current, therefore enhanced current ratio (I_ON/I_OFF). Here channel length is also dependent on bias condition. In ON-state the effective channel length is equal to the length of overlap region of top and bottom gates. In OFF-state, the effective channel length is the length excluding overlap region between top and bottom gate.

Figure 1.2 shows a comparison between ON-state and OFF-state of the transistor. Different characteristics have been drawn with and without pocket region. The proposed AJ-DGMOSFET with heavily doped pocket region shows better ratio in comparison to AJ-DGMOSFET without a doped pocket region.

Table 1.1 Comparison of existing MOSFET structures.

Ref.	Existing MOSFET structure and methodology	Electrical performance and applications
[2]	Ge pockets are inserted in SOI JLT	Reduces the lattice temperature. The channel length is 20 nm.
[3]	Gate all around junctionless MOSFET with source and drain extension	The highly doped regions have also led to an increase in I-ON current magnitude by 70%.
[4]	Gate engineering using double-gate MOSFET	The sub-threshold slope is decreased by 1.61% and ON/OFF current ratio is increased by 17.08% and DIBL is decreased by 4.52%. The channel length is 20 nm.
[5]	Gate material engineering and drain/source Extensions	Improves the RF and analog performance. The figure of merit is also increased compared to the conventional double-gate junctionless MOSFET. The channel length is 100 nm.
[6]	Inducing source and drain extensions electrically	Suppresses short-channel effects for the channel length less than 50 nm and also suppresses hot electron effects.
[7]	Nanogap cavity is formed by the process of etching gate oxide in the channel from both the sides of source and drain	Detecting biomolecules such as DNA, enzymes, cells etc using dielectric modulation technique. The channel length is 100 nm.
[8]	Graded channel dual material gate junctionless (GC-DMGJL) MOSFET	The GC-DMGJL MOSFET gives high drain current and transconductance and also reduces short-channel effects. The channel length is 30 nm.
[9]	Black phosphorus is integrated with the junctionless recessed MOSFET	Structure drain current increases up to 0.3 mA. The off current reduces, improvement in subthreshold slope. The channel length is 44 nm.
[10]	Fully depleted tri material double-gate MOSFET is used	Improvement in the RF performance, linearity and analog performance compared to the DM-DG MOSFET and single material DG MOSFET. The channel length is 35 nm.
[11]	Pocket region is constructed near the source and drain region and is heavily doped	Good immunity from short-channel effects and can meet the specifications of OFF-state current and ON-state current. The channel length is 100 nm.
[12]	A transparent gate recessed channel is used	Enhancement of cut-off frequency by 42% and oscillator frequency is increased by 32%. The channel length is 30nm.
[13]	MOSFET with asymmetrical gate to improve the functioning of the device	Decrease in subthreshold slope (68 mV/dec) and drain induced barrier lowering (65 mV/V). The channel length is 20 nm.
[14]	6-T SRAM cell using silicon on insulator	The area of the junctionless transistor-based 6-T SRAM cell using silicon on inductor is 6.9 μm-cube and that of the conventional structure is 11.3 μm -cube.
[15]	Short-channel dual metal gate with recessed source and drain SOI MOSFET	This device provides high on current, low DIBL value. The channel length is 30 nm -300nm.
[16]	Dual Material Surrounding Gate MOSFET to suppress short-channel effects	DMSG MOSFET (SCEs) more efficient as compared to a conventional SMSG MOSFET
[17]	Misalignment effect introduced by the asymmetrical source and drain	The region which is non-overlapped produces extra series resistance and weak control over the channel, while the additional overlapped region produces extra overlap capacitance and supply to ground leakage current through gate
[18]	Optimized the design of the gate all around MOSFET and compared it with the double gate MOSFET	GAA structure reduced the DIBL value to 81.44 mV/V when compared to the double-gate MOSFET. The ON-state current is increased and OFF-state current is reduced.
[19]	The deviation in the oxide thickness between the two gates is considered small. A surface potential solution is used for symmetric double-gate MOSFET for initial trial approximation for approaching surface potential solution for asymmetric double-gate MOSFET.	Different parameters of MOSFET like drain current, 5channel current, transconductance, gate capacitances and the effect of oxide thickness on these parameters are determined.
[20]	Performance analysis of junctionless double-gate MOSFET based 6T SRAM with gate stack configuration	The use of high k dielectric material in the junctionless DG-MOSFET shows improvement in static noise margin. Scaling down of gate length degrades the stability.
[21]	Simulation of junctionless double-gate MOSFET with symmetrical side gates. With the presence of side gates the channel present under the front gate, is electrically insulated from the drain voltage resulting to electron shielding.	The DIBL and SS values improved using the side gates. The drain voltage effect on the channel is reduced so it becomes easy for the gate to have more control over the channel.
[22]	A structure of double-gate MOSFET with symmetrical insulator packets for improving the SCEs. In this, insulator packets were inserted between the channel junction and source/ drain ends	Hot electron reliability improves. There is an improvement in the DIBL value and ON/OFF-state current ratio.

Figure 1.1 2D view of AJ-DGMOSFET.

Figure 1.4 shows the performance of MOSFET when different gate contacts are used like aluminium, polysilicon and copper. MOSFET shows better performance when polysilicon is used as a gate contact. Metal gates like Aluminium and copper operate at voltages 3V to 5V. The lowering of operating voltages leads to the use of polysilicon gate contact. From the graph we can observe at lower operating voltages polysilicon gate contact gives better performance because the OFF-state current is low.

Figure 1.2 I_d versus V_gs plot of AJ-DGMOSFET.

Figure 1.3 Id Versus Vgs plot with different oxide region material.

The proposed JL-DG MOSFET has ratio of 10¹³ which is higher than other existing structures. The calculation of SCE parameters like SS and DIBL is also a deciding factor for device performance. The proposed device show SS value of 59 mV/ decade and DIBL of 13.4 mV/V. Both SS and DIBL values are less than other existing transistors. Therefore, heavily doped AJ-DG MOSFET has superior ON/OFF performances.

Figure 1.4 I_d versus V_gs Plot of different gate contact material.

Figure 1.5 JL-DG MOSFET with cavity region.