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Vedic mathematics is one of ancient Indian mathematics computes mathematical operations and is actively based on formulas for fast computations “Urdhva-Tiryakbhyam”. Sutra is more generic and appropriate for multiplication. The meaning of Urdhva-Tiryakbhyam is “vertically and crosswise”. The significant advantage of the Urdhva-Tiryakbhyam multiplication method is that it requires at most logical “AND” operations, arrangements of half adder (HA) and full adder (FA) to accomplish multiplication [6, 7]. Partial products require in multiplication generated in Parallel, minimizes computation time. In Figure 2.1, darkened circles present the bits of “multiplier and multiplicand”; arrows present bits to multiplied compute each bits of product.

A Vedic sutra is a multiplication algorithm employed into the Vedic multiplier. These sutras were used to multiply decimal numbers traditionally; however, these sutras find application into multiplying binary and hexadecimal numbers equally. Urdhva Tiryakbhyam, Nikhimal sutram and Anurupyena sutras are the most preferred technique among the Vedic algorithm for reduction of delay, power and cell resources with a higher number of inputs [8–10]. Vedic multiplication is a fast method of calculation that provides unique techniques of calculation with half of simple rule and principle.

Here we have implemented multiplication of 8-bit number X[7:0] and Y[7:0]. Here X[0] presents the least significant bits (LSB), X[7] is the most significant bits (MSB), generate product P[15:0]. Each partial product P[0] to P[15] is calculated from equation given below. Equation (2.1) to (2.15) present the partial product P[0] to P[15], which is calculated in the internal multiplication algorithm. Which in turn produces the final product shown in equation (2.16). Internal carry bit created during computation given in as c[1] to c[30]. Carry bits made for P[14] and P[15] are neglected, because of the superfluous. Multiplication implemented with the addition of internal signals on each stage. Partial product P1-P15 shown the internal carry generation, which propagated to the next steps. Product P2-P15 requires additional hardware to add 4 bits since full adders can add only 3 bits. The addition of higher input performed using compressors with compressor architectural addition of more than three inputs implemented with reduced architecture and improved speed [11].

Figure 2.1 Multiplication of two 8-bit number with Urdhwa-Tiryakbhyam Sutra [28].