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The 16x16 Vedic Multiplier requires 666 cells to implement this project, and the area which is obtained by cells is 5967, and the net area is “zero” as shown in Table 2.6. The total area in which it is accomplished is 5967, and there is no wire load for this Vedic Multiplier.

16-bit multiplier needs 666 cells to implement. Here unwanted sub-threshold current which is leakage of power in 60576.57 nW. The dynamic power of 16-bit multiplier to complete product are 444556.31 nW and the total power obtained to 505132.87 nW as shown in Table 2.7.

Table 2.6 Cell area of 16x16 vedic multiplier.

Instance	Cells	Cell area	Net area	Total area	Wire load
16-bit VM	666	5967	0	5967	<none> (D)

Table 2.7 Power constraints of 16x16 vedic multiplier.

Instance	Cells	Leakage power (nW)	Dynamic power (nW)	Total power (nW)
16-bit VM	666	60576.57	444556.31	505132.87

Table 2.8 Time constraint of 16x16 vedic multiplier.

Pin	Type	Fanout	Load (fF)	Slew (ps)	Delay (ps)	Arrival (ps)
p[30]	out port				0	5476 R

Table 2.9 Comparison of multiplier architecture.

8-bit Multiplier	Leakage power (μW)	Dynamic power (micro μW)	Total power (μW)	Delay (ns)	Cell count	Cell area
Vedic Multiplier	13.44	86.42	99.86	2.637	139	1517
Booth Multiplier [21]	5.69	324.53	330.22	3.75	214	5115
Wallace Tree Multiplier [21]	5.6263	655.55	661.17	3.02	248	1470
Dadda Multiplier [21]	5.62	655.807	2661.47	2.56	266	1330

Here pin p[30] defines that it is the last output pin of 16x16 Vedic Multiplier and type defines whether it is input port or output port. The longest path arrival time form input to pin p[30] is 5476 ps shown in Table 2.8.

The present work of 8-bit Vedic multiplier is compared with the existing different architecture of multiplier, shown in Table 2.9 in terms of power, delay and cell area. It is observed that the Dadda multiplier needs a large number of nets that require a lower area than the Wallace tree multiplier. Booth requires a lower number of cells but the total area increases to approximately three- to four-fold compare to the Wallace tree and Dadda multiplier [17–19]. Since the booth multiplication algorithm requires multiple time shifting-adding greater number of wire resources.

Vedic multiplier replaces the underlying cell by compressors logic, made up of adder block. Utilization of compressor greatly reduces the wiring resource save area. The leakage power of the Vedic multiplier is larger than other compare multipliers but shows very low dynamic power consumption. Dadda multiplier requires maximum power to reduce the delay 2.56ns. A Vedic multiplier attains significant reduction in dynamic power requirement and delay of multiplication architecture. Cell count of VM is 139 which is much smaller than other multipliers.