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An efficient productive strategy for multiplication based on Urdhva Tiryakbhyam Sutra (Algorithm) in view of Vedic mathematics is implemented in this paper with Verilog HDL. Here a fast 8-bit multiplier is implemented that incorporates architecture of compressor. Compressor is a derived structure of full adder and half adder, map multiple input to lesser number of output signals. Hierarchical multiplier structure and shows the computational speed by offered by Vedic methods. Essential inspiration of this work is to decrease the delay in complex multiplication achieve 2.637 ns. We can deduce that the compressor-based architecture of Vedic math’s multiplier is more favorable than conventional multipliers and preferred in complex algorithm implementation. Hence, we have concluded that Instance Power usage of 8x8 Vedic Multiplier is 40.48% and 16x16 Vedic Multiplier is 62.22%. The Net Power usage of 8x8 Vedic Multiplier is 82.24%, and the 16x16 Vedic Multiplier is 86.85%.