Читать книгу Design and Development of Efficient Energy Systems - Группа авторов - Страница 33

In Figure 2.10, 15;5 compressor made of seven full adders, three half adders, and two 7:3 compressors. The working principle of this compressor is understood as input (X1-X3) inputs applied to the full adder (FP11). (X4-X6) inputs are provided to full adder (FP2), (X7-X9) inputs are given to full adder (FP3), (X10-X12) inputs are given to full adder (FP4), (X13-X15) inputs are given to full adder (FP5), (X16-X18) inputs are given to full adder (FP6) and the last two inputs (X19-X20) are given to half adder (HP1). The sum obtained from this (FP1), (FP2), (FP3), (FP4), (FP5), (FP6), and (HP1) is given to 7:3 compressor (CP1) and carry is given to another 7:3 compressor (CP2). The sum obtained from 7:3 compressor (CP1) is the output Y1of the compressor.

Figure 2.10 Compressor 20 to 5.

The output carry1 of 7:3 compressor (CP1) and the sum obtained from 7:3 compressor (CP2) is given to half adder (HP2). The sum which is obtained from half adder (HP2) is taken as output Y2. The carry of half adder (HP2), carry2 of 7:3 compressor (CP1), and carry1 of 7:3 compressor (CP2) given to full adder (FP7). The sum obtained from full adder (FP7) taken as output Y3. The carry of this full adder (FP7) and carry2 of 7:3 compressor (CP2) given to half adder (HP2). The sum obtained from half adder (HP3) is taken as output Y4 and carry is taken as output Y5. Different compressor blocks are integrated to develop the architecture using the Boolean equation.

Figure 2.11 Behavioral simulation of 8x8 VM.

Figure 2.11 presents the simulated waveform of which obtained while we implemented the 8x8 Vedic Multiplier. We have given input for a specific time, and it goes to the end till which we have mentioned stop in the test bench. Here a is 8-bit input and b is 8-bit input, and we are getting 16 bit as output, and it is represented in p. The multiplier is implemented with Verilog HDL using the Xilinx ISE tool. The synthesis result obtained from vertex-4 FPGA. An 8-bit VM requires 418 slices, 729 LUT and 67 IOB shown in Table 2.2. A similar effect is verified with cadence NCSIM and the implementation result confirmed with RTL compiler at gpdk 180nm technology. The simulation result shows that

Table 2.2 FPGA utilization summary report.

Device utilization summary
Logic utilizations	Used	Available	Utilization
Slices	418	1672	4%
4 input LUTs	729	17344	4%
Bounded IOBs	67	250	26%

The case I Input A=8’d136 and B=8’d119 result in multiplier values p=16’h16184.

Case II Input A=8’d141 and B=8’d124 result in multiplier values p=16’h17484.

Case III Input A=8’d145 and B=8’d129 result in multiplier values p=16’h18834.