Читать книгу Design and Development of Efficient Energy Systems - Группа авторов - Страница 34

The performance parameter of 8-bit VM is judged by power consumption, delay, and area report obtained by the cadence RTL compiler. Completed implementation of an 8-bit Vedic multiplier is through the combinatorial block. The usage of the compressor reduces the requirement of resources. As the number of the logic gate but increases the interconnecting wires. Similarly, area requirements to interface multiple compressors significantly enhance the area and delay. In this section area, power and delay are presented due to logical resources and wires.