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Table 2.3 presents the cell area requirement of the 8x8 Vedic Multiplier. Cell area report models the number of the basic cell requires to the design. To implement this project 139 cells are required, and the area which is obtained by cells is 1517, and the net area is “zero”. The total area which is accomplished is 1517, and there is no Wire Load for this Vedic Multiplier.

Table 2.3 Cell area of 8x8 vedic multiplier.

Instance	Cells	Cell area	Net area	Total area	Wire load
Vedic Multiplier	139	1517	0	1517	<none> (D)

Table 2.4 Power constraints of 8x8 vedic multiplier.

Instance	Cells	Leakage power(nW)	Dynamic power(nW)	Total power(nW)
vedicmultiplier	139	13442.07	86424.01	99866.08

Table 2.5 Time constraint of 8x8 vedic multiplier.

Pins	Type	Fan out	Load (fF)	Slew (ps)	Delay (ps)	Arrival (ps)
p[14]	out port				0	2637 R

An instance of an 8-bit VM named Vedic multiplier requires 139 cells in this project; there is an unwanted sub-threshold current which is leakage of power in 13422.07nW (Nano Watt). Dynamic power, a part of power that consumed while the inputs are active, obtained value is 86424.01 nW and the total power which is obtained for this 8x8 Vedic Multiplier is 99866.08 nW shown in Table 2.4.

Here pin p[14] defines that it is the last output pin of 8x8 Vedic Multiplier and type defines whether it is input port or output port. The longest path arrival time (AT) of signal is calculated as the latency for a signal to arrive at point of consideration, for this project is 2637 ps shown in Table 2.5.