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High-speed power and low-power multiplication are the fundamental blocks for high-speed processor architecture. It is hard to realize both high-speed and low-power architecture (VLSI tradeoff). There is various multiplier architecture available in the literature. Basically, the multiplier is complete by repeated addition; a full adder is a basic unit of the multiplier, cell area increases proportionally with the number of input increases. Switching power increases with interconnection among the cells. The present work of the Vedic multiplier is focused on reducing the cell count by utilizing a compressor block into the design. The compressor is a combination of multiple adder block. It accepts multiple inputs to perform addition and map the result into a lower number of the output signal.

Vedic arithmetic is derived from Vedas (books of shrewdness) [1]. It is a chunk of Sthapatya-Veda (book on structural building and design), which is an Upaveda (supplement) of Atharva Veda. It incorporated the hypothesis of standard numerical terms having a place in number belonging, geometry (plane, co-ordinate), trigonometry, quadratic conditions, factorization, and even math. His Holiness Jagadguru Shankaracharya Bharati Krishna Teerthaji Maharaja (1884-1960) consolidated his work and introduced it as a scientific clarification. Swamiji consolidated 16 sutras (formulae) and 16 Upa sutras (sub-formulae) from Atharva Veda as shown in Table 2.1. Vedic mathematics consists of the special technique of computations based on natural principles. Mathematical problems in trigonometric, algebra, and geometry can be solved simply. The Vedic method contains 16 sutras, describing natural ways of computing. The beauty of Vedic mathematics is that it simplifies complex calculations. The Vedic method shows effective methods of implementation of multiplication with higher bits for the science and engineering field.

Table 2.1 Sutra in Vedic mathematics [2–5].

Sutras	Properties
Anurupye Shunyamanyat	One is in proportion, other is zero
ChalanaKalanabyham	Closeness and distinction
EkadhikinaPurven	By one more than the past one
kanyunenaPurvena	By one is greater than previous one
Gunakasamuchyah	Elements of the whole are equivalent to the quantity of components
Gunitasamuchyah	The product of sum (POS) is equivalent to sum of product (SOP)
NikhilamNavatashcaramamDashatah	All from 9 and previous from 10
ParaavartyaYojayet	Interchange and modify
Puranapuranabyham	Completion of the non-completion
Sankalana	Addition and subtraction
ShesanyankenaCharamena	Remainders
ShunyamSaamyasamuccaye	Sum is zero
Sopaantyadvayamantyam	Twice and ultimate
Urdhva-tiryakbhyam	Vertical - crosswise
Vyashtisamanstih	Part – entire
Yaavadunam	Extent of deficiency