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The hardware architecture of 8x8 multiplier explained below is dependent on Urdhva-Tiryagbhyam. The advantages of VM algorithms found as generation of partial product and performed synchronously. It enhanced the parallel processing and preferred for the implementation of the binary multiplier. An 8x8 Vedic multiplication block diagram, presented in Figure 2.2 implemented as a binary equation is given below. Each stage generates partial product, term as carrying. This carry input added with the next step of a partial product. Here requires adder can accept multiple data together. A full adder is a basic unit that can provide three data together. A compressor derived from the adder used to implement numerous inputs [12–16]. A 4:3 compressor accepts four inputs and maps the result into three output signals. 8x8 VM hardware architecture requires adding 20 input bits together, which is implemented with 20:5 compressor.

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Figure 2.2 Block diagram of 8*8 multiplier.

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