Читать книгу Antenna-in-Package Technology and Applications - Duixian Liu - Страница 15

As the technology of choice for integration of digital circuitry, a complementary metal oxide semiconductor (CMOS) was proposed for the integration of analog circuitry for radio frequency (RF) applications in the mid‐1980s, aiming for the ultimate goal of full integration of an entire wireless system on a chip [1]. In the mid‐1990s, the first fully integrated CMOS transceiver for data communications in the 900‐MHz industrial, scientific and medical (ISM) band was successfully demonstrated [2]. Since then, CMOS has been the enabler for wireless systems on chip (SoCs) operating from a few to tens of gigahertz. Figure 1.1 shows the die micrograph of the first wireless SoC, a 2.4‐GHz CMOS mixed RF analog–digital Bluetooth radio announced at the International Solid‐State Circuits Conference (ISSCC) 2001 [3]. The die size is 40.1 mm². It integrates on the same substrate a low intermediate frequency (IF) receiver, a Cartesian transmitter, a baseband processer, an advanced reduced‐instruction set‐computer machine (ARM) processor, flash memory, and random‐access memory (RAM).

Full SoC integration is clearly not suitable in all cases. In fact, the radio chip is separate in many cases. Traditionally, silicon germanium (SiGe) seems to have been preferred to CMOS for analog RF. Figure 1.2 shows the die micrographs of the first SiGe 60‐GHz transmitter and receiver disclosed at ISSCC 2006 [4]. The die sizes are 4.0 × 1.6 mm² and 3.4 × 1.7 mm², respectively. The level of integration achieved in these chips was high then for 60‐GHz radios. The transmitter chip integrates a power amplifier, image‐reject driver, IF‐to‐RF up‐mixer, IF amplifiers, quadrature baseband‐to‐IF mixers, phase‐locked loop (PLL), and frequency tripler. The receiver chip includes an image‐reject low‐noise amplifier, RF‐to‐IF mixer, IF amplifiers, quadrature IF‐to‐baseband mixers, PLL, and frequency tripler. The input/output (I/O) pads are peripheral, with 60 on the transmitter and 53 on the receiver chips.

Figure 1.1 Micrograph of the first 2.4‐GHz CMOS wireless SoC, a Bluetooth radio (from [3], © 2001 IEEE, reprinted with permission).Figure 1.2 Photographs of the first 60‐GHz SiGe radio chipset: (a) transmitter and (b) receiver (from [4], © 2006 IEEE, reprinted with permission).

The emergence of wireless SoCs or single‐chip radios called for compatible antenna solutions, which provided an excellent opportunity for researchers of prepared minds to seriously explore the feasibility of integrating an antenna in a chip package using packaging materials and processes in the late 1990s, leading to the development of antenna‐in‐package (AiP) technology [5]. This chapter recounts how AiP technology has been developed to its current state. Section 1.2 describes the idea of AiP with respect to the ideas of antenna on chip (AoC), antenna in module (AiM), antenna on board (AoB), and active integrated antenna (AIA). Section 1.3 reviews the early attempts to explore the idea of AiP. Section 1.4 reflects on the milestones in the development of the idea of AiP into a mainstream antenna and packaging technology. Finally, Section 1.5 gives concluding remarks.