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Design and Optimization of Heterostructure Double Gate Tunneling Field Effect Transistor for Ultra Low Power Circuit and System
ОглавлениеGuenifi Naima1* and Shiromani Balmukund Rahi2
1LEA Electronics Department, University Mostefa Benboulaid of Batna 2, Batna, Algeria
2Department of Electrical Engineering, Indian Institute of Technology Kanpur, India
Abstract
Tunnel FET, a quantum device nowadays known as the best suitable candidate for the future of ultra-low-power applications, due to a distinct current transport mechanism, known as band-to-band (B2B) tunneling. This device is recommended as a replacement for conventional Metal-Oxide-Semiconductor (MOS) FET due to limitation of subthreshold slope (i.e., SS < 60 mV/ dec at T = 300 K), a bottleneck issue for modern low-power design and process engineers. In this chapter, we have mainly focused on double gate (DG) TFET, having band engineering and high - k dielectrics. Due to successful implementation of both these scientific suggestions, the DG -TFET shows improved device characteristics in terms of current efficiency (ION), leakage current (IOFF), subthreshold slope (SS), ambipolar current (Iamb), transconductance (gm), transconductance efficiency (gm/IDS), switching response time (ιd), and power delay product (PDP). In this chapter, the transfer (Id -Vg), C - V and RF characteristics DG -TFET are investigated in detail.
Keywords: TFET, MOSFET, BTBT, SCEs, Kane’s model, high - k, subthreshold (SS), Ultra low power