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Nowadays TFET devices have become the most popular switching device among semiconductor players. This is due to the fact that TFET devices have capability to overcome the limitation conventional MOSFET, i.e., smaller subthreshold slope (< 60mV/decade at room temperature) and sharp switching capability. Another useful feature of TFET is process and materials compatibility with conventional CMOS technology. This compatibility of TFET devices and TFET-based technology is the key feature, which will reduce the product development cost and fulfil the requirement of ultra-low power in terms of time, cast and quality.

It is basically a gate controlled, p-i-n based field effect switching device, commonly worked under reversed base condition [3–8]. The switching behavior of TFET is completely different than conventional MOSFETs. In summary, if the applied voltage on gate terminal, VGS < VTH. TFET is ideally in an off position. Ideally, no current can flow in the device due to large tunneling distance. Note that, VTH is the minimum required voltage for device required to tunneling of charge carriers from source to drain via channel. This minimum required voltage in TFET causes proper band alignment for tunneling of charges from source to drain via charnel. This VTH, i.e., threshold voltage is not the same as for conventional MOSFETs [26–28].

If the applied voltage on gate terminal (i.e., VGS) increases sufficiently then VTH, i.e., VGS > VTH. TFET is in the on position. Now the device is switched from the off-state to the on-state. It has been evident that the electric field inside the tunneling region has become significantly large due to increased gate voltage, VGS. This causes a band shifting due to applied forces, and results in reduction of tunneling barrier (λ). Thus, the gradual enhancement of the gate bias (VGS) degrades the sufficient barrier width (λ) and causes an increased tunneling of carriers.

Figure 2.2 and Figure 2.3 show the energy band diagram estimated for homo structure DG -TFET and hetero structure DG -TFET shown in Figure 2.1. As shown in Figure 2.2 and Figure 2.3, when applied gate voltage, V_GS = 0.0 V, the device is in an off-state with large tunnel barrier width λ, and therefore the charge carrier, electrons do not have enough energy to move from the valance band of the source to the conduction band of the channel. As the gate voltage VGS increases, on application of sufficiently high gate voltage (i.e., V_GS = 1.5 V and V_DS = 0.5 V), the tunneling barrier (λ) reduces significantly and the device switches to on-state, as indicated in Figure 2.2 and Figure 2.3. From Figure 2.2 and Figure 2.3, it is clearly observed that hetero structure double gate DG -TFET, having smaller tunneling width λ than homo structure DG -TFET. For hetero and homo structured double gate TFET, tunneling with λ_hetero ~ 0.05 µm and λ_homo ~ 0.056 µm is calculated by obtained simulation. This is because of misalignment between two bandgap materials Si (Eg~1.12eV) and GaAs (Eg~1.52eV).

Figure 2.2 Energy band-diagram (OFF-State and ON-State) for homo DG -TFET contains source, channel and drain region silicon materials.

Figure 2.3 Energy band-diagram (OFF-State and ON-State) for hetero structure DG -TFET contains source, channel and drain region Si, GaAs semiconductor materials.

Table 2.2 summarizes the extracted design parameters for DG - TFET, shown in Figure 2.1(a) and Figure 2.1(b). As shown in Table 2.2, all the design parameters of DG - TFET such as I_ON, I_OFF, I_ON/I_OFF and SS have improved significantly as per requirements while ambipolar current (I_amb) is reduced drastically.