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Practically, the estimation of device characteristics and performance of TFET is still time consuming and costly due to lack of rapid advancement in technology. The conventional procedure commonly used in electronic industry known as “Modeling and Simulation” is adopted for DG - TFET device. This is practically a more adequate procedure and a relatively inexpensive way to design electronic circuit and system.

The results shown in this chapter are taken from Silvaco ATLAS^TM simulation. For accurate estimation of device performance, the non-local BTBT (BBT.NONLOCAL) model has been used to estimate the tunneling current in DG - TFET. In addition, SRH (Shokely-Read-Hall) recombination, auger recombination, trap-assisted tunneling (TAT) and band gap narrowing (BGN) model has been incorporated.

Figure 2.1 shows the schematic view of double gate TFET (DG - TFET). As shown in Figure 2.1 in hetero DG - TFET, source and channel region contains heavily doped semiconductors with two different band gap semiconductors, Si (Eg~1.12eV) and GaAs (Eg~1.52eV). As per state-of-art of bandgap engineering, at the interface region of Si/GaAs, the effective bandgap (E_{g effective}) is slightly smaller than homo Si or GaAs. According to Equation 2.1, this reduced Eg _effective increases the tunneling probability, results larger tunneling current in hetero TFET than homo TFET. The representative schematic diagram of hetero and homo DG - TFET is shown in Figure 2.1(a) and Figure 2.1(b) containing Si/GaAs/GaAs and Si/Si/Si semiconductor materials in source, channel and the drain region, respectively. For the improvement of electrostatic behavior DG - TFET, suggested by K. Boucart et al. [26], here HfO2 dielectric has been used as a key gate material. As shown in Figure 2.1 the DG -TFET device, which is calibrated with simulated structure with a channel length (L_ch) of 50 nm, ultra-thin body (t_si) of 10 nm.

Figure 2.1 Schematic of double gate (a) hetero structure (b) homostructure tunnel FET.

Table 2.1 summarizes all device physical parameters used during device simulation. For double gate TFET, shown in Figure 2.1(a) and Figure 2.1(b), gate dielectric, 2.0 nm thickness with HfO2 (high-k) has been used. The thickness of silicon channel has been taken to be 10.0 nm, while whole channel length, i.e., from source to drain region, has been taken as 50.0 nm. A uniform doping of 1.0 × 10²⁰ cm^–3 and 5.0 × 10¹⁸ cm^–3 have been used for the drain and source regions, respectively. The work function for gate material corresponding to this region is set to 5.2 eV.

All simulation results of the DG – TFET presented in the chapter and design have been carried out using Silvaco/ATLAS device simulator version 3.1.20.1.R in Windows 7 operating system environment. The fine meshing tunneling in the regions where BTBT mainly takes place were defined. Mesh size = 5 × 10^-4 μm at interface source/channel and mesh size = 10^-3 μm far of interface. To obtain a better convergence and a low computation time, Newton’s numerical method based on iteration was chosen. To analyse in high-frequency (HF) performance parameter of device the gate of transistor was attacked with a - signal AC of low amplitude at a frequency equals to 1 MHz. All analysis was performed in 3D under engineering logiciel MATLAB and Excel.

Table 2.1 Device design parameters for simulation of (a) hetero structure (b) homostructure tunneling FET.

Physical parameters	Nomenclature	Numerical value
ϕM	Work function (eV)	5.2
NS	Doping levels for source (cm-3)	1.1 × 1020
ND	Doping level for Drain (cm-3)	5.1 × 1018
NC	Doping level for channel (cm-3)	1015
tox	Gate oxide material thickness (nm)	2.0
Lt	Total length of the device (nm)	250.0
Lch	Channel length (nm)	50.0
tSi	Silicon film thickness (nm)	10.0
LS/LD	Source and drain lengths (nm)	100.0