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The drain current (I_DS) in the DG -TFET, which is estimated by B2B tunneling and governed by popularly known as Kane’s model [18, 19]. The tunneling probability of charge carried in tunnel-based devices is estimated by the known WKB model written as Equation 2.1 [25–27]. These popular models show strong dependency of tunneling transport phenomena on device geometry, materials and induced electric field inside the device. Both popular Equations (2.1 & 2.2) provide sufficient facilities in term of process and technology to optimize device characteristics and performance by choice of appropriate device geometry and materials.

Table 2.2 Lists of computed electrical parameters of double gate (a) hetero structure (b) homo structure tunneling FET.

Design parameter	High - k dielectric (HfO2 ≈ 25)
Homo - DG -TFET	Hetero - DG -TFET
ION (A/µm)	4.0 × 10-6	4.0 × 10-6
IOFF (A/µm)	1.0 × 10-18	1.0 × 10-20
ION/IOFF	4.0 × 1012	4.0 × 1014
SS (mV/dec)	39. 68	34.25
Iamb (A/µm)	5.0 × 10-11	1.0 × 10-19

The most common technique suggested by a device expert is gate dielectric engineering. In this technique, instead of SiO₂ (k ≈ 3.9), other popular gate dielectric materials, for example, Si₃N₄ (k ≈ 12), ZrO₂ (k ≈ 24) and HfO₂ (k ≈ 25) are commonly used. The used high - k dielectric materials, instead of SiO₂, increases the internal electric field, improves the electrostatic performance of TFETs [19, 26]. Figure 2.4 and Figure 2.5 show the impact of high - k gate dielectic on DG -TFET. Both Figures (2.4 & 2.5) indicate an even higher on-current (ION) and decreased subthreshold swing (SS) with higher high - k dielectric materials. Table 2.3 and Table 2.4, have the extracted device design parameters of DG - TFET. During investigation and from Table 2.3 and Table 2.4, it has been observed that the various design parameters such as ION, IOFF, ION/IOFF, SS, Iamb for both homo and hetero DG -TFET have been improved. But hetero DG -TFET shows superiority than homo DG -TFET due to improved electric field with reduced effective tunneling bandgap. As shown in Figure 2.2 and Figure 2.3, this is possible due to improved electric field inside the device and reduced effective bandgap inside the tunneling region at the interface of Si/GaAs. This effective reduced bandgap in case of hetero DG -TFET, reduces the tunneling window as shown in Figure 2.3.

Figure 2.4 Transfer characteristic of homo structure double gate TFET.

Figure 2.5 Transfer characteristic of hetero structure double gate TFET.

Table 2.3 Lists of computed design parameters of the homo structure DG -TFET with various gate dielectric materials.

Design parameters	Gate dielectric material (Homo structure Si/Si/Si)
HfO2 (k ≈ 25)	ZrO2 (k ≈ 24)	Si3N4 (k ≈ 12)	SiO2 (k ≈ 3.9)
Vth(V)	0.55	0.55	0.80	0.85
SS(mV/decade)	39.68	39.71	42.73	45.00
ION(A/μm)	4.0 × 10-6	3.90 × 10-6	5.00 × 10-7	1.00 × 10-7
IOFF(A/μm)	1.00 × 10-18	1.00 × 10-18	1.00 × 10-18	1.00 × 10-18
ION/IOFF	4.00 × 1012	3.90 × 1013	5.0 × 1011	1.00 × 1011

Table 2.4 Lists of computed design parameters of the hetero structure DG -TFET with various gate dielectric materials.

Design parameters	Gate dielectric materials (Hetero structure Si/GaAs/GaAs)
HfO2 (k ≈ 25)	ZrO2 (k ≈ 24)	Si3N4 (k ≈ 12)	SiO2 (k ≈ 3.9)
Vth (V)	0.5	0.5	0.7	0.75
SS(mV/decade)	34.25	34.27	40.65	44.25
ION(A/μm)	4.00 × 10-6	3.90 × 10-6	2.00 × 10-7	2.00 × 10-8
IOFF(A/μm)	1.00 × 10-20	1.00 × 10-19	1.00 × 10-19	1.00 × 10-19
ION/IOFF	4.00 × 1014	3.90 × 1014	2.0 × 1012	2.00 × 1011

Ideally in off-state, there is no current flow in TFET, due to large tunneling width (λ). But in practical case, few charge particles pass the λ, in off-state condition, resulting in smaller IOFF current. But practically the magnitude of the off current in case of TFET is smaller than MOSFETs. On the other hand, when applied VGS sufficiently large, tunneling barrier λ, between source and channel reduce significantly and sufficient number of charge particles to pass from source to drain via channel, resulting in ION current. Interestingly, when applied VGS is negatively high, the tunneling barrier width between the channel and drain narrows, which induces tunneling current [17–22]. The particular state of TFET device is known as ambipolar state and the amount of current following in this state is known as ambipolar (Iamb), as shown in Figure 2.6. Figure 2.6 is dedicated for study of ambimiparity behaviour of DG -TFET, an unwanted conduction known as malfunction. Figure 2.6 shows the comparision of ambipolar property of homo and hetero structure DG - TFET. The result shows that, DG -TFET with adopted technology shows suppression of the ambipolar current (Iamb) without deteriorating analog, and transient performance. From Figure 2.6, it has been observed, with the help of 2-D. TCAD simulation that, the ambipolar current (Iamb) is suppressed by 10⁸ order of magnitude in proposed Si/GaAs/GaAs hetero DG - TFET as compared to Si/Si/Si homo DG -TFET up to the applied gate voltage of V_GS = − 3.0V the step of gate voltage was taken equal to 0.5V.

Figure 2.6 Comparision of ambipolar current vs. applied gate drive voltage (V_GS) for homo and hetero structure double gate tunnel FET.

Figure 2.7 shows the impact of drain voltage (VDS) on DG -TFET. From Figure 2.7, it is clearly evident that applied drain voltage (VDS) has negligible impact on TFET performance. This is strong evidence that TFET is almost free from DIBL (Drain Induced Barrier Lower). This is a strong recommendation for replacement of conventional low-power device, circuit and system with TFETs and TFET-based circuit and system design.

The transconductance (gm) represents amplification ability of device and important design parameter of circuit and system design. It is defined as the slope of the transfer characteristic. The gm value can be calculated by mathematical Equation 2.4. Figure 2.8 shows the variation of gm versus applied VGS. From Figure 2.8, it has been observed that g_m value decreases with decrease of applied gate voltage, VGS that is due smaller tunneling current at lower VGS.

Figure 2.7 Device transfer characteristics for double gate N- TFET hetero structure with a variation of V_DS plot (a) linear (b) Semilog.

Figure 2.8 Sensitivity of transconductance (gm) with applied gate voltage (VGS) and comperision between double gate hetero and homo structure DG -TFET.

Figure 2.9 shows 3D visualization of transconductance, cut-frequency and applied gate voltage (gm, f_T, VGS). From Figure 2.9 and Figure 2.10, clearly, it has been observed that the hetero and homo structures: transconductance, cut-frequency (gm, f_T) increase rapidly as external applied gate voltage V_GS increases. The maximum gm-hetero value of the hetero DG -TFET ~1.6 μS/μm and f_T-hetero ~ 0.65 GHz and gm-homo ~1.4 μS/μm f_T-homo ~ 0.55GHz. The gm-hetero > gm-homo due to smaller effective tunneling barrier width (i.e. λ _hetero ~ 0.05 µm< λ _hetero ~0 .056 µm), shown in Figure 2.2 and Figure 2.3

Figure 2.9 3D - transconductance (gm), cut-frequency (fT) and applied gate drive voltage (VGS) of hetero DG -TFET.

Figure 2.10 3D - transconductance (g_m), cut-frequency (f_T) and applied gate drive voltage (V_GS) of homo DG -TFET.

(2.4)

Figure 2.11 shows the variation of exiting capacitances of hetero and homo DG -TFET with applied gate voltage (VGS). The gate-gate capacitance is mainly composed of two capacitances between, gate-drain (Cgd), gate-source (Cgs) and gate-gate (Cgg). The gatesource capacitance (C_gs) is lower because of the presence of the tunnel effect, the gate-drain capacitance (C_gd) is a dominant capacitance due to the accumulation of the electrons of the source-channel and collected by the drain region.

Figure 2.11 The varibility of C-V characteristics with applied gate drive voltage (V_GS) and compersion of homo and hetero structure DG -TFET.

As an important circuit design parameter, the cut-off frequency (f_T) is used to evaluate the frequency characteristics of electronic devices. It can be obtained by the ratio of gm to Cgg, with following relation, Equation 2.5

(2.5)

Figure 2.11 shows a variability study of available capacitance on DG -TFET with applied VGS. From Figure 2.11, it has been observed that, as the applied gate voltage increases (VGS), the cut-off frequency (f_T) increases to reach its maximum, then with increasing Cgg, it goes down, when the gate voltage (VGS) reaches 2.0 V the cut-off frequency (f_T) becomes constant. This is because the on-state current (I_ON) and its derivative, g_m value increase with the electronic B2B tunneling. The cut-off frequency (f_T) of hetero DG-TFET is much larger than that of homo (i.e. f_{T - hetero}~ 0.65 GHz > f_{T - homo}~ 0.55GHz); this is due to smaller Cgg of hetero DG - TFET and the larger of the gm value than homo DG -TFET. This observation is verified by obtained results, shown in Figure (2.8 & 2.11). From these figures, it has been observed that the obtained results predicts decreased gate capacitance with decreased applied gate voltage (VGS), as depicted in Figure 2.11, which gives the variation of the gate capacitance with VGS. It should be noted that the capacitances of TFET is bias-dependent. That is to say, the decrement rate of the gate capacitance with frequency is bias-dependent.

The gain bandwidth (GBW) product is an important design parameter in the analysis of RF characteristics, which can be calculated by the Equation 2.6. All the results of the simulation are summarized in Table 2.5. As shown in Figure 2.12 and Figure 2.13, there is a variation of gm and GWB versus applied gate voltage (V_GS) i.e., (gm, GWB vs. V_GS) and compression for homo and hetero DG -TFET. The variation of g_m, GWB with V_GS is similar to variation of g_m, f_T with V_GS from Figure 2.12 and Figure 2.13; clearly, it has been observed that hetero and homo structures transconductance, gain bandwidth product (g_m, GWB) increase rapidly as external applied gate voltage V_GS increases.

(2.6)

The maximum, GWB _hetero ~ 0.66 GHz and GWB _homo ~ 0.49 GHz. Another design parameter, the transconductance efficiency (g_m/I_DS) of for DG - TFET, shown in Figure 2.14, has been calculated. The factor g_m/I_DS plays a primary role in the behavior of the device; it shows the rate of amplification of the transistor. The g_m/I_DS of TFETs is dependent on several factors such as drain current (I_DS) and SS, barrier tunnel with (λ) i.e., applied gate voltage (V_GS). Figure 2.14 shows the g_m/I_DS dependence of applied gate voltage (V_GS). As shown in Figure 2.14, g_m/I_DS increases until it reaches a maximum value (around the threshold voltage). Figure 2.14 shows (g_m/I_DS) _hetero > (g_m/I_DS) _homo. The maximum value of g_m/I_DS ~ 285.84 V^-1 for hetero structure while ~ 241.01 V^-1 for homo respectively.

Table 2.5 Lists of the computed RF parameters of the hetero and homo DG-TFET.

High-k gate dielectric HfO2 (≈ 25)	VDS = 0.5 V
Cut-off frequency (fT)	GBW (GHz)
Hetero structure	~ 0.65 GHz	0.66 GHz
Homo structure	~ 0.55GHz	0.49 GHz

Figure 2.12 3D - transconductance (g_m), GBW and applied gate drive voltage (V_GS) of hetero DG -TFET.

Figure 2.13 3D - transconductance (g_m), GBW and applied gate drive voltage (V_GS) of homo DG -TFET.

Another important performance parameter for RF analysis is transit time (ι_d) estimated by Equation 2.7. The Equation 2.7 indicates that the delay time is inversely proportional to the cut-off frequency (f_T) i.e., the cut-off frequency increases as the transition time decreases. It is the time taken by the charge carriers (electrons) to cross the channel. Figure 2.15 shows the dependency of applied gate drive voltage (V_GS) vs. delay time (ι_d) and compression of delay time between homo and hetero structure DG - TFET.

Figure 2.14 Transconductance efficiency, gm/IDS with applied gate voltage (VGS) and comparison between double gate hetero and homo structure DG -TFET.

Figure 2.15 Sensitivity of delay time with applied gate voltage (V_GS) and comparison between double gate hetero and homo structure DG -TFET.

From Figure 2.15, it has been evident that ι_{d- hetero}< ι_{d- homo} and shows, dealy time with applied gate voltage (V_GS) is less sensitive than homo DG-TFT. This is a strong recommendation for low power applications.

(2.7)

Figure 2.16 shows the sensitivity of power delay product (PDP) with applied V_GS and a comparison between double gate hetero and homo structure DG -TFET. In term of digital circuit design, power delay product is an important design parameter, correlated with the energy efficiency. From Figure 2.16, it has been observed that PDP is strongly affected with the variation of gate drive voltage (V_GS). Lowering the supply voltage (V_DS = 0.5V), lowers the PDP in hetero structure DG -TFET.

Figure 2.16 Sensitivity of power delay product (PDP) with applied gate voltage (V_GS) and comparison between double gate hetero and homo structure DG -TFET.