Читать книгу Digital System Design using FSMs - Peter D. Minns - Страница 25

Figure 1.11 shows an example of a single‐pule circuit FSM.

The idea here is to develop a circuit based on the FSM that will produce a single output pulse at its output P whenever its input s is taken to logic 1. The FSM is to be clock driven so it also has an input clock. An additional output L is used to indicate that a P pulse has been produced so the user can see effect of ‘fast’ pulses.

The block diagram of this circuit is shown in Figure 1.11.

Figure 1.11 Block diagram of single pulse with memory FSM.

Figure 1.12 shows a suitable state diagram.

Figure 1.12 State diagram for single pulse with memory FSM.

In this state diagram the sling (loop /s going to and from s0) indicates that while input s is logic 0 (/s) the FSM will remain in state s0 regardless of how many clock pulses are applied to the FSM. Only when input s goes to logic 1 will the FSM move from state s0 to s1, and then only when a clock pulse arrives. Once in state s1, the FSM will set its output P to logic 1, and on the next clock pulse the FSM will move from state s1 to s2.

The reason why the FSM will stay in state s1 for only one clock pulse is because in state s1 the transition from this state‐to‐state s2 occurs on a clock pulse only. Once the FSM arrives in state s2, it will remain there whilst input s = 1. As soon as input s goes to logic 0 (/s) the FSM will move back to state s0 on the next clock pulse.

Since the FSM remains in state s1 for only a single clock pulse, and since P = 1 only in state s1, the FSM will produce a single output pulse.

Note in the FSM state diagram that each state has a unique state identity: s0, s1, and s2.

Also note that each state has been allocated a unique combination of flip‐flop states, for example:

 State s0 uses the flip‐flop combination A = 0 B = 0, e.g. both flip‐flops reset.

 State s1 uses the flip‐flop combination A = 1 B = 0, e.g. flip‐flop A is set.

 State s2 uses the flip‐flop combination A = 0 B = 1, e.g. flip‐flop A is reset, flip‐flop B is set.

Now move on to Frame 1.12.