Читать книгу Digital System Design using FSMs - Peter D. Minns - Страница 34

Modify the state diagram to make it produce a 101 sequence of clock pulses (in the same manner as shown in Frames 1.15and 1.16. Also, arrange for the P output pulse in state s3 to be conditional on a new input called x. If x = 0, the FSM should produce the output sequence 100 at P. If x = 1, the output sequence at P should be 101.

The modified state diagram is shown in Figure 1.21.

Figure 1.21 Modified state diagram with output P as a Mealy output.

In Figure 1.21, the clock is used as a qualifier in states s1 and s3 so that the output P is only logic 1 in these two states. However, state s3 has an additional qualifier x, so in s3 P = 1 only when in s3 and then only if input signal x is true in s3.

Then in state s3, the output P will only obtain a clock pulse if the x input happens to be logic 1.

You can see that if x = 0 then, when the input s is raised to logic 1, the FSM will produce the sequence 100 at output P. Therefore, P = s1 + s3·x. If x = 1 then, when s is raised to logic 1, the FSM will produce a 101 sequence at the output P.

This FSM is an example of a Mealy FSM since the output P is a function of both the state and the inputs clock and x, i.e. both clock and x are fed forward to the output decoding logic.

The reader could easily modify the FSM so that the 100 sequence at P was produced if x = 1, and the 101 sequence produced if x = 0. Therefore, now:

 Produce the Boolean equation for P in state s3 that would satisfy this requirement.

 Then assign a unit distance code to the state diagram; see Frames 1.12and 1.13.

 Finally, when you have done that, try producing a timing diagram of the modified FSM.

When you’ve finished, turn to Frame 1.20.