Читать книгу Digital System Design using FSMs - Peter D. Minns - Страница 36

The solution is, of course, based on the secondary state assignments used, so your solution could well be different if you have used a different SSV pattern.

In this solution (Figure 1.23), the author has deliberately arranged for the x input to change to logic 0 inside of the clock pulse equal to 1 in state s3 just to illustrate the effect that this would have on the output P. You can see that the output pulse on P is not a full clock high period.

Figure 1.23 Timing diagram showing the effect of input x on output P.

This is a very realistic event since the outside world input x (and, indeed, any outside world input) can occur at any time.

Turn to Frame 1.22.