Читать книгу Digital System Design using FSMs - Peter D. Minns - Страница 26

Frame 1.12

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Let’s continue with the one‐pulse design.

The flip‐flop outputs are seen to define each state. If we could see nothing more than the A and B outputs of the two flip‐flops, we could tell what state the FSM was in by the output logic levels on each flip‐flop.

We could also tell in which state the output P was to be logic 1, i.e. in state s1 where the flip‐ flop output logic levels are A = 1 and B = 0.

Therefore, the output P = A/B. (Remember, AB is used to indicate the logical AND operation used in Boolean algebra.)

So we now see that the flip‐flops are used to provide a unique identity for each state.

We also see that, since each state can be defined in terms of the flip‐flop output states, the outside world outputs can also be defined in terms of the flip‐flop output states since the outside worlds output states themselves are a function of these states.

L is logic 1 in states s1 and s2 and is defined in terms of the flip‐flop outputs A/B + /AB.

Therefore, L = A/B + /AB = A/B + /AB. No Boolean reduction is possible in this case.

The allocation of unique values of flip‐flop outputs to each state is rather an arbitrary process. In theory, we can use any values so long as each state has a unique combination. This means that we cannot have more than one state with the flip‐flop values of, say, A/B (i.e. both states cannot have the same value).

In practice it is common to assign flip‐flop values so that the transition between each state involves only one flip‐flop changing state. This is known as ‘following a unit distance pattern’: only one flip‐flop changes state.

The above example does not use a unit distance pattern since there are two flip‐flop changes between states s1 and s2. However, the reader will be going on to make use of the unit distance code idea.

The reader could also make the single‐pulse state diagram (Figure 1.12) follow a unit distance pattern by adding an extra state. This extra state could be inserted between states s2 and s0, having the same output for P as state s0. In the state diagram the new state would also have the value of L, the same as that in state s2, since the reader does not want L to change until s goes to 0.

Try re‐drawing the state diagram with this additional state and assign a unit distance pattern to the flip‐flops.

When you have done this, go to Frame 1.13.

Digital System Design using FSMs

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